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Move the v3 resource allocator to v2. 

Major changes:
1. Separate resource allocation into:
	A. Read Resources
	B. Avoid fixed resources (constrain limits)
	C. Allocate resources
	D. Set resources

Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources.  All fixed resources will end up outside (above or below) 
the allocated resources.

Domains usually start with base = 0 and limit = 2^address_bits - 1.

I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources.  Some platforms may want to change that, but I didn't
want to break anyone's board.

Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.

Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Myles Watson 2009-07-02 18:56:24 +00:00
parent 2468331952
commit 29cc9eda20
62 changed files with 1508 additions and 1591 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

49
src/cpu/amd/sc520/sc520.c
View File

@ -62,9 +62,27 @@ void sc520_enable_resources(struct device *dev) {
} }
static void sc520_read_resources(device_t dev)
{
struct resource* res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x400UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static struct device_operations cpu_operations = { static struct device_operations cpu_operations = {
.read_resources = pci_dev_read_resources, .read_resources = sc520_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = sc520_enable_resources, .enable_resources = sc520_enable_resources,
.init = cpu_init, .init = cpu_init,
@ -78,25 +96,6 @@ static const struct pci_driver cpu_driver __pci_driver = {
.device = 0x3000 .device = 0x3000
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
printk_spew("%s\n", __func__);
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -184,14 +183,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
printk_spew("%s\n", __func__);
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
#if 0 #if 0
void sc520_enable_resources(device_t dev) { void sc520_enable_resources(device_t dev) {
@ -219,7 +210,7 @@ static struct device_operations pci_domain_ops = {
* If enable_resources is set to the generic enable_resources * If enable_resources is set to the generic enable_resources
* function the whole thing will hang in an endless loop on * function the whole thing will hang in an endless loop on
* the ts5300. If this is really needed on another platform, * the ts5300. If this is really needed on another platform,
* something is conceptionally wrong. * something is conceptually wrong.
*/ */
.enable_resources = 0, //enable_resources, .enable_resources = 0, //enable_resources,
.init = 0, .init = 0,

48
src/cpu/emulation/qemu-x86/northbridge.c
View File

@ -9,23 +9,6 @@
#include "chip.h" #include "chip.h"
#include "northbridge.h" #include "northbridge.h"
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -70,7 +53,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
extern uint64_t high_tables_base, high_tables_size; extern uint64_t high_tables_base, high_tables_size;
#endif #endif
static void pci_domain_set_resources(device_t dev) static void cpu_pci_domain_set_resources(device_t dev)
{ {
static const uint8_t ramregs[] = { static const uint8_t ramregs[] = {
0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57
@ -127,15 +110,34 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) static void cpu_pci_domain_read_resources(struct device *dev)
{ {
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); struct resource *res;
return max;
pci_domain_read_resources(dev);
/* Reserve space for the IOAPIC. This should be in the Southbridge,
* but I couldn't tell which device to put it in. */
res = new_resource(dev, 2);
res->base = 0xfec00000UL;
res->size = 0x100000UL;
res->limit = 0xffffffffUL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
/* Reserve space for the LAPIC. There's one in every processor, but
* the space only needs to be reserved once, so we do it here. */
res = new_resource(dev, 3);
res->base = 0xfee00000UL;
res->size = 0x10000UL;
res->limit = 0xffffffffUL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
IORESOURCE_ASSIGNED;
} }
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = cpu_pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = cpu_pci_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,

21
src/cpu/ppc/ppc4xx/pci_domain.c
View File

@ -7,27 +7,6 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <console/console.h> #include <console/console.h>
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {

2
src/devices/cardbus_device.c
View File

@ -77,8 +77,6 @@ static void cardbus_size_bridge_resource(device_t dev, unsigned index)
resource = find_resource(dev, index); resource = find_resource(dev, index);
if (resource) { if (resource) {
min_size = resource->size; min_size = resource->size;
compute_allocate_resource(&dev->link[0], resource,
resource->flags, resource->flags);
/* Allways allocate at least the miniumum size to a /* Allways allocate at least the miniumum size to a
* cardbus bridge in case a new card is plugged in. * cardbus bridge in case a new card is plugged in.
*/ */

726
src/devices/device.c
View File

@ -12,6 +12,7 @@
* Copyright (C) 2005-2006 Tyan * Copyright (C) 2005-2006 Tyan
* (Written by Yinghai Lu <yhlu@tyan.com> for Tyan) * (Written by Yinghai Lu <yhlu@tyan.com> for Tyan)
* Copyright (C) 2005-2006 Stefan Reinauer <stepan@openbios.org> * Copyright (C) 2005-2006 Stefan Reinauer <stepan@openbios.org>
* Copyright (C) 2009 Myles Watson <mylesgw@gmail.com>
*/ */
/* /*
@ -43,12 +44,6 @@ struct device *all_devices = &dev_root;
/** Pointer to the last device */ /** Pointer to the last device */
extern struct device **last_dev_p; extern struct device **last_dev_p;
/** The upper limit of MEM resource of the devices.
* Reserve 20M for the system */
#define DEVICE_MEM_HIGH 0xFEBFFFFFUL
/** The lower limit of IO resource of the devices.
* Reserve 4k for ISA/Legacy devices */
#define DEVICE_IO_START 0x1000
/** /**
* @brief Allocate a new device structure. * @brief Allocate a new device structure.
@ -71,25 +66,25 @@ device_t alloc_dev(struct bus *parent, struct device_path *path)
spin_lock(&dev_lock); spin_lock(&dev_lock);
/* Find the last child of our parent */ /* Find the last child of our parent. */
for(child = parent->children; child && child->sibling; ) { for (child = parent->children; child && child->sibling; /* */ ) {
child = child->sibling; child = child->sibling;
} }
dev = malloc(sizeof(*dev)); dev = malloc(sizeof(*dev));
if (dev == 0) { if (dev == 0)
die("DEV: out of memory.\n"); die("DEV: out of memory.\n");
}
memset(dev, 0, sizeof(*dev)); memset(dev, 0, sizeof(*dev));
memcpy(&dev->path, path, sizeof(*path)); memcpy(&dev->path, path, sizeof(*path));
/* Initialize the back pointers in the link fields */ /* Initialize the back pointers in the link fields. */
for (link = 0; link < MAX_LINKS; link++) { for (link = 0; link < MAX_LINKS; link++) {
dev->link[link].dev = dev; dev->link[link].dev = dev;
dev->link[link].link = link; dev->link[link].link = link;
} }
/* By default devices are enabled */ /* By default devices are enabled. */
dev->enabled = 1; dev->enabled = 1;
/* Add the new device to the list of children of the bus. */ /* Add the new device to the list of children of the bus. */
@ -132,16 +127,12 @@ static void read_resources(struct bus *bus)
{ {
struct device *curdev; struct device *curdev;
printk_spew("%s read_resources bus %d link: %d\n", printk_spew("%s %s bus %x link: %d\n", dev_path(bus->dev), __func__,
dev_path(bus->dev), bus->secondary, bus->link); bus->secondary, bus->link);
/* Walk through all of the devices and find which resources they need. */ /* Walk through all devices and find which resources they need. */
for (curdev = bus->children; curdev; curdev = curdev->sibling) { for (curdev = bus->children; curdev; curdev = curdev->sibling) {
unsigned links;
int i; int i;
if (curdev->have_resources) {
continue;
}
if (!curdev->enabled) { if (!curdev->enabled) {
continue; continue;
} }
@ -151,26 +142,10 @@ static void read_resources(struct bus *bus)
continue; continue;
} }
curdev->ops->read_resources(curdev); curdev->ops->read_resources(curdev);
curdev->have_resources = 1;
/* Read in subtractive resources behind the current device */ /* Read in the resources behind the current device's links. */
links = 0; for (i = 0; i < curdev->links; i++)
for(i = 0; i < curdev->resources; i++) { read_resources(&curdev->link[i]);
struct resource *resource;
unsigned link;
resource = &curdev->resource[i];
if (!(resource->flags & IORESOURCE_SUBTRACTIVE))
continue;
link = IOINDEX_SUBTRACTIVE_LINK(resource->index);
if (link > MAX_LINKS) {
printk_err("%s subtractive index on link: %d\n",
dev_path(curdev), link);
continue;
}
if (!(links & (1 << link))) {
links |= (1 << link);
read_resources(&curdev->link[link]);
}
}
} }
printk_spew("%s read_resources bus %d link: %d done\n", printk_spew("%s read_resources bus %d link: %d done\n",
dev_path(bus->dev), bus->secondary, bus->link); dev_path(bus->dev), bus->secondary, bus->link);
@ -183,13 +158,15 @@ struct pick_largest_state {
int seen_last; int seen_last;
}; };
static void pick_largest_resource(void *gp, static void pick_largest_resource(void *gp, struct device *dev,
struct device *dev, struct resource *resource) struct resource *resource)
{ {
struct pick_largest_state *state = gp; struct pick_largest_state *state = gp;
struct resource *last; struct resource *last;
last = state->last; last = state->last;
/* Be certain to pick the successor to last */
/* Be certain to pick the successor to last. */
if (resource == last) { if (resource == last) {
state->seen_last = 1; state->seen_last = 1;
return; return;
@ -206,21 +183,22 @@ static void pick_largest_resource(void *gp,
if (!state->result || if (!state->result ||
(state->result->align < resource->align) || (state->result->align < resource->align) ||
((state->result->align == resource->align) && ((state->result->align == resource->align) &&
(state->result->size < resource->size))) (state->result->size < resource->size))) {
{
state->result_dev = dev; state->result_dev = dev;
state->result = resource; state->result = resource;
} }
} }
static struct device *largest_resource(struct bus *bus, struct resource **result_res, static struct device *largest_resource(struct bus *bus,
unsigned long type_mask, unsigned long type) struct resource **result_res,
unsigned long type_mask,
unsigned long type)
{ {
struct pick_largest_state state; struct pick_largest_state state;
state.last = *result_res; state.last = *result_res;
state.result_dev = 0; state.result_dev = NULL;
state.result = 0; state.result = NULL;
state.seen_last = 0; state.seen_last = 0;
search_bus_resources(bus, type_mask, type, pick_largest_resource, search_bus_resources(bus, type_mask, type, pick_largest_resource,
@ -233,7 +211,7 @@ static struct device *largest_resource(struct bus *bus, struct resource **result
/* Compute allocate resources is the guts of the resource allocator. /* Compute allocate resources is the guts of the resource allocator.
* *
* The problem. * The problem.
* - Allocate resources locations for every device. * - Allocate resource locations for every device.
* - Don't overlap, and follow the rules of bridges. * - Don't overlap, and follow the rules of bridges.
* - Don't overlap with resources in fixed locations. * - Don't overlap with resources in fixed locations.
* - Be efficient so we don't have ugly strategies. * - Be efficient so we don't have ugly strategies.
@ -244,133 +222,125 @@ static struct device *largest_resource(struct bus *bus, struct resource **result
* space for devices with programmable addresses. This easily handles * space for devices with programmable addresses. This easily handles
* everything except bridges. * everything except bridges.
* *
* - PCI devices are required to have thier sizes and their alignments * - PCI devices are required to have their sizes and their alignments
* equal. In this case an optimal solution to the packing problem * equal. In this case an optimal solution to the packing problem
* exists. Allocate all devices from highest alignment to least * exists. Allocate all devices from highest alignment to least
* alignment or vice versa. Use this. * alignment or vice versa. Use this.
* *
* - So we can handle more than PCI run two allocation passes on * - So we can handle more than PCI run two allocation passes on bridges. The
* bridges. The first to see how large the resources are behind * first to see how large the resources are behind the bridge, and what
* the bridge, and what their alignment requirements are. The * their alignment requirements are. The second to assign a safe address to
* second to assign a safe address to the devices behind the * the devices behind the bridge. This allows us to treat a bridge as just
* bridge. This allows me to treat a bridge as just a device with * a device with a couple of resources, and not need to special case it in
* a couple of resources, and not need to special case it in the * the allocator. Also this allows handling of other types of bridges.
* allocator. Also this allows handling of other types of bridges.
* *
*/ */
void compute_resources(struct bus *bus, struct resource *bridge,
void compute_allocate_resource( unsigned long type_mask, unsigned long type)
struct bus *bus,
struct resource *bridge,
unsigned long type_mask,
unsigned long type)
{ {
struct device *dev; struct device *dev;
struct resource *resource; struct resource *resource;
resource_t base; resource_t base;
unsigned long align, min_align; base = round(bridge->base, bridge->align);
min_align = 0;
base = bridge->base;
printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d\n", printk_spew( "%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx\n",
dev_path(bus->dev), dev_path(bus->dev), __func__,
(bridge->flags & IORESOURCE_IO)? "io": (type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
(bridge->flags & IORESOURCE_PREFETCH)? "prefmem" : "mem", "prefmem" : "mem",
base, bridge->size, bridge->align, bridge->gran); base, bridge->size, bridge->align, bridge->gran, bridge->limit);
/* We want different minimum alignments for different kinds of /* For each child which is a bridge, compute_resource_needs. */
* resources. These minimums are not device type specific for (dev = bus->children; dev; dev = dev->sibling) {
* but resource type specific. unsigned i;
struct resource *child_bridge;
if (!dev->links)
continue;
/* Find the resources with matching type flags. */
for (i = 0; i < dev->resources; i++) {
unsigned link;
child_bridge = &dev->resource[i];
if (!(child_bridge->flags & IORESOURCE_BRIDGE) ||
(child_bridge->flags & type_mask) != type)
continue;
/* Split prefetchable memory if combined. Many domains
* use the same address space for prefetchable memory
* and non-prefetchable memory. Bridges below them
* need it separated. Add the PREFETCH flag to the
* type_mask and type.
*/ */
if (bridge->flags & IORESOURCE_IO) { link = IOINDEX_LINK(child_bridge->index);
min_align = log2(DEVICE_IO_ALIGN); compute_resources(&dev->link[link], child_bridge,
type_mask | IORESOURCE_PREFETCH,
type | (child_bridge->flags &
IORESOURCE_PREFETCH));
} }
if (bridge->flags & IORESOURCE_MEM) {
min_align = log2(DEVICE_MEM_ALIGN);
} }
/* Make certain I have read in all of the resources */ /* Remember we haven't found anything yet. */
read_resources(bus); resource = NULL;
/* Remember I haven't found anything yet. */ /* Walk through all the resources on the current bus and compute the
resource = 0; * amount of address space taken by them. Take granularity and
* alignment into account.
/* Walk through all the devices on the current bus and
* compute the addresses.
*/ */
while ((dev = largest_resource(bus, &resource, type_mask, type))) { while ((dev = largest_resource(bus, &resource, type_mask, type))) {
resource_t size;
/* Do NOT I repeat do not ignore resources which have zero size.
* If they need to be ignored dev->read_resources should not even
* return them. Some resources must be set even when they have
* no size. PCI bridge resources are a good example of this.
*/
/* Make certain we are dealing with a good minimum size */
size = resource->size;
align = resource->align;
if (align < min_align) {
align = min_align;
}
/* Propagate the resource alignment to the bridge register */ /* Size 0 resources can be skipped. */
if (align > bridge->align) { if (!resource->size) {
bridge->align = align;
}
if (resource->flags & IORESOURCE_FIXED) {
continue; continue;
} }
/* Propogate the resource limit to the bridge register */ /* Propagate the resource alignment to the bridge resource. */
if (resource->align > bridge->align) {
bridge->align = resource->align;
}
/* Propagate the resource limit to the bridge register. */
if (bridge->limit > resource->limit) { if (bridge->limit > resource->limit) {
bridge->limit = resource->limit; bridge->limit = resource->limit;
} }
#warning This heuristic should be replaced by real devices with fixed resources.
/* Artificially deny limits between DEVICE_MEM_HIGH and 0xffffffff */ /* Warn if it looks like APICs aren't declared. */
if ((bridge->limit > DEVICE_MEM_HIGH) && (bridge->limit <= 0xffffffff)) { if ((resource->limit == 0xffffffff) &&
bridge->limit = DEVICE_MEM_HIGH; (resource->flags & IORESOURCE_ASSIGNED)) {
printk_err("Resource limit looks wrong! (no APIC?)\n");
printk_err("%s %02lx limit %08Lx\n", dev_path(dev),
resource->index, resource->limit);
} }
if (resource->flags & IORESOURCE_IO) { if (resource->flags & IORESOURCE_IO) {
/* Don't allow potential aliases over the /* Don't allow potential aliases over the legacy PCI
* legacy pci expansion card addresses. * expansion card addresses. The legacy PCI decodes
* The legacy pci decodes only 10 bits, * only 10 bits, uses 0x100 - 0x3ff. Therefore, only
* uses 100h - 3ffh. Therefor, only 0 - ff * 0x00 - 0xff can be used out of each 0x400 block of
* can be used out of each 400h block of io * I/O space.
* space.
*/ */
if ((base & 0x300) != 0) { if ((base & 0x300) != 0) {
base = (base & ~0x3ff) + 0x400; base = (base & ~0x3ff) + 0x400;
} }
/* Don't allow allocations in the VGA IO range. /* Don't allow allocations in the VGA I/O range.
* PCI has special cases for that. * PCI has special cases for that.
*/ */
else if ((base >= 0x3b0) && (base <= 0x3df)) { else if ((base >= 0x3b0) && (base <= 0x3df)) {
base = 0x3e0; base = 0x3e0;
} }
} }
if (((round(base, align) + size) -1) <= resource->limit) { /* Base must be aligned. */
/* base must be aligned to size */ base = round(base, resource->align);
base = round(base, align);
resource->base = base; resource->base = base;
resource->flags |= IORESOURCE_ASSIGNED; base += resource->size;
resource->flags &= ~IORESOURCE_STORED;
base += size;
printk_spew("%s %02lx * [0x%08Lx - 0x%08Lx] %s\n", printk_spew("%s %02lx * [0x%llx - 0x%llx] %s\n",
dev_path(dev), dev_path(dev), resource->index,
resource->index,
resource->base, resource->base,
resource->base + resource->size - 1, resource->base + resource->size - 1,
(resource->flags & IORESOURCE_IO) ? "io" : (resource->flags & IORESOURCE_IO) ? "io" :
(resource->flags & IORESOURCE_PREFETCH)? "prefmem": "mem"); (resource->flags & IORESOURCE_PREFETCH) ?
} "prefmem" : "mem");
#if CONFIG_PCIE_CONFIGSPACE_HOLE
#warning Handle PCIe hole differently...
if (base >= 0xf0000000 && base < 0xf4000000) {
base = 0xf4000000;
}
#endif
} }
/* A pci bridge resource does not need to be a power /* A pci bridge resource does not need to be a power
* of two size, but it does have a minimum granularity. * of two size, but it does have a minimum granularity.
@ -378,13 +348,317 @@ void compute_allocate_resource(
* know not to place something else at an address postitively * know not to place something else at an address postitively
* decoded by the bridge. * decoded by the bridge.
*/ */
bridge->size = round(base, bridge->gran) - bridge->base; bridge->size = round(base, bridge->gran) -
round(bridge->base, bridge->align);
printk_spew("%s compute_allocate_resource %s: base: %08Lx size: %08Lx align: %d gran: %d done\n", printk_spew("%s %s_%s: base: %llx size: %llx align: %d gran: %d limit: %llx done\n",
dev_path(bus->dev), dev_path(bus->dev), __func__,
(bridge->flags & IORESOURCE_IO) ? "io" : (bridge->flags & IORESOURCE_IO) ? "io" :
(bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem", (bridge->flags & IORESOURCE_PREFETCH) ? "prefmem" : "mem",
base, bridge->size, bridge->align, bridge->gran, bridge->limit);
}
/**
* This function is the second part of the resource allocator.
*
* The problem.
* - Allocate resource locations for every device.
* - Don't overlap, and follow the rules of bridges.
* - Don't overlap with resources in fixed locations.
* - Be efficient so we don't have ugly strategies.
*
* The strategy.
* - Devices that have fixed addresses are the minority so don't
* worry about them too much. Instead only use part of the address
* space for devices with programmable addresses. This easily handles
* everything except bridges.
*
* - PCI devices are required to have their sizes and their alignments
* equal. In this case an optimal solution to the packing problem
* exists. Allocate all devices from highest alignment to least
* alignment or vice versa. Use this.
*
* - So we can handle more than PCI run two allocation passes on bridges. The
* first to see how large the resources are behind the bridge, and what
* their alignment requirements are. The second to assign a safe address to
* the devices behind the bridge. This allows us to treat a bridge as just
* a device with a couple of resources, and not need to special case it in
* the allocator. Also this allows handling of other types of bridges.
*
* - This function assigns the resources a value.
*
* @param bus The bus we are traversing.
* @param bridge The bridge resource which must contain the bus' resources.
* @param type_mask This value gets anded with the resource type.
* @param type This value must match the result of the and.
*/
void allocate_resources(struct bus *bus, struct resource *bridge,
unsigned long type_mask, unsigned long type)
{
struct device *dev;
struct resource *resource;
resource_t base;
base = bridge->base;
printk_spew("%s %s_%s: base:%llx size:%llx align:%d gran:%d limit:%llx\n",
dev_path(bus->dev), __func__,
(type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
"prefmem" : "mem",
base, bridge->size, bridge->align, bridge->gran, bridge->limit);
/* Remember we haven't found anything yet. */
resource = NULL;
/* Walk through all the resources on the current bus and allocate them
* address space.
*/
while ((dev = largest_resource(bus, &resource, type_mask, type))) {
/* Propagate the bridge limit to the resource register. */
if (resource->limit > bridge->limit) {
resource->limit = bridge->limit;
}
/* Size 0 resources can be skipped. */
if (!resource->size) {
/* Set the base to limit so it doesn't confuse tolm. */
resource->base = resource->limit;
resource->flags |= IORESOURCE_ASSIGNED;
continue;
}
if (resource->flags & IORESOURCE_IO) {
/* Don't allow potential aliases over the legacy PCI
* expansion card addresses. The legacy PCI decodes
* only 10 bits, uses 0x100 - 0x3ff. Therefore, only
* 0x00 - 0xff can be used out of each 0x400 block of
* I/O space.
*/
if ((base & 0x300) != 0) {
base = (base & ~0x3ff) + 0x400;
}
/* Don't allow allocations in the VGA I/O range.
* PCI has special cases for that.
*/
else if ((base >= 0x3b0) && (base <= 0x3df)) {
base = 0x3e0;
}
}
if ((round(base, resource->align) + resource->size - 1) <=
resource->limit) {
/* Base must be aligned. */
base = round(base, resource->align);
resource->base = base;
resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED;
base += resource->size;
} else {
printk_err("!! Resource didn't fit !!\n");
printk_err(" aligned base %llx size %llx limit %llx\n",
round(base, resource->align), resource->size,
resource->limit);
printk_err(" %llx needs to be <= %llx (limit)\n",
(round(base, resource->align) +
resource->size) - 1, resource->limit);
printk_err(" %s%s %02lx * [0x%llx - 0x%llx] %s\n",
(resource->
flags & IORESOURCE_ASSIGNED) ? "Assigned: " :
"", dev_path(dev), resource->index,
resource->base,
resource->base + resource->size - 1,
(resource->
flags & IORESOURCE_IO) ? "io" : (resource->
flags &
IORESOURCE_PREFETCH)
? "prefmem" : "mem");
}
printk_spew("%s%s %02lx * [0x%llx - 0x%llx] %s\n",
(resource->flags & IORESOURCE_ASSIGNED) ? "Assigned: "
: "",
dev_path(dev), resource->index, resource->base,
resource->size ? resource->base + resource->size - 1 :
resource->base,
(resource->flags & IORESOURCE_IO) ? "io" :
(resource->flags & IORESOURCE_PREFETCH) ? "prefmem" :
"mem");
}
/* A PCI bridge resource does not need to be a power of two size, but
* it does have a minimum granularity. Round the size up to that
* minimum granularity so we know not to place something else at an
* address positively decoded by the bridge.
*/
bridge->flags |= IORESOURCE_ASSIGNED;
printk_spew("%s %s_%s: next_base: %llx size: %llx align: %d gran: %d done\n",
dev_path(bus->dev), __func__,
(type & IORESOURCE_IO) ? "io" : (type & IORESOURCE_PREFETCH) ?
"prefmem" : "mem",
base, bridge->size, bridge->align, bridge->gran); base, bridge->size, bridge->align, bridge->gran);
/* For each child which is a bridge, allocate_resources. */
for (dev = bus->children; dev; dev = dev->sibling) {
unsigned i;
struct resource *child_bridge;
if (!dev->links)
continue;
/* Find the resources with matching type flags. */
for (i = 0; i < dev->resources; i++) {
unsigned link;
child_bridge = &dev->resource[i];
if (!(child_bridge->flags & IORESOURCE_BRIDGE) ||
(child_bridge->flags & type_mask) != type)
continue;
/* Split prefetchable memory if combined. Many domains
* use the same address space for prefetchable memory
* and non-prefetchable memory. Bridges below them
* need it separated. Add the PREFETCH flag to the
* type_mask and type.
*/
link = IOINDEX_LINK(child_bridge->index);
allocate_resources(&dev->link[link], child_bridge,
type_mask | IORESOURCE_PREFETCH,
type | (child_bridge->flags &
IORESOURCE_PREFETCH));
}
}
}
#if CONFIG_PCI_64BIT_PREF_MEM == 1
#define MEM_MASK (IORESOURCE_PREFETCH | IORESOURCE_MEM)
#else
#define MEM_MASK (IORESOURCE_MEM)
#endif
#define IO_MASK (IORESOURCE_IO)
#define PREF_TYPE (IORESOURCE_PREFETCH | IORESOURCE_MEM)
#define MEM_TYPE (IORESOURCE_MEM)
#define IO_TYPE (IORESOURCE_IO)
struct constraints {
struct resource pref, io, mem;
};
static void constrain_resources(struct device *dev, struct constraints* limits)
{
struct device *child;
struct resource *res;
struct resource *lim;
int i;
printk_spew("%s: %s\n", __func__, dev_path(dev));
/* Constrain limits based on the fixed resources of this device. */
for (i = 0; i < dev->resources; i++) {
res = &dev->resource[i];
if (!(res->flags & IORESOURCE_FIXED))
continue;
/* PREFETCH, MEM, or I/O - skip any others. */
if ((res->flags & MEM_MASK) == PREF_TYPE)
lim = &limits->pref;
else if ((res->flags & MEM_MASK) == MEM_TYPE)
lim = &limits->mem;
else if ((res->flags & IO_MASK) == IO_TYPE)
lim = &limits->io;
else
continue;
/* Is it already outside the limits? */
if (res->size && (((res->base + res->size -1) < lim->base) ||
(res->base > lim->limit)))
continue;
/* Choose to be above or below fixed resources. This
* check is signed so that "negative" amounts of space
* are handled correctly.
*/
if ((signed long long)(lim->limit - (res->base + res->size -1)) >
(signed long long)(res->base - lim->base))
lim->base = res->base + res->size;
else
lim->limit = res->base -1;
}
/* Descend into every enabled child and look for fixed resources. */
for (i = 0; i < dev->links; i++)
for (child = dev->link[i].children; child;
child = child->sibling)
if (child->enabled)
constrain_resources(child, limits);
}
static void avoid_fixed_resources(struct device *dev)
{
struct constraints limits;
struct resource *res;
int i;
printk_spew("%s: %s\n", __func__, dev_path(dev));
/* Initialize constraints to maximum size. */
limits.pref.base = 0;
limits.pref.limit = 0xffffffffffffffffULL;
limits.io.base = 0;
limits.io.limit = 0xffffffffffffffffULL;
limits.mem.base = 0;
limits.mem.limit = 0xffffffffffffffffULL;
/* Constrain the limits to dev's initial resources. */
for (i = 0; i < dev->resources; i++) {
res = &dev->resource[i];
if ((res->flags & IORESOURCE_FIXED))
continue;
printk_spew("%s:@%s %02lx limit %08Lx\n", __func__,
dev_path(dev), res->index, res->limit);
if ((res->flags & MEM_MASK) == PREF_TYPE &&
(res->limit < limits.pref.limit))
limits.pref.limit = res->limit;
if ((res->flags & MEM_MASK) == MEM_TYPE &&
(res->limit < limits.mem.limit))
limits.mem.limit = res->limit;
if ((res->flags & IO_MASK) == IO_TYPE &&
(res->limit < limits.io.limit))
limits.io.limit = res->limit;
}
/* Look through the tree for fixed resources and update the limits. */
constrain_resources(dev, &limits);
/* Update dev's resources with new limits. */
for (i = 0; i < dev->resources; i++) {
struct resource *lim;
res = &dev->resource[i];
if ((res->flags & IORESOURCE_FIXED))
continue;
/* PREFETCH, MEM, or I/O - skip any others. */
if ((res->flags & MEM_MASK) == PREF_TYPE)
lim = &limits.pref;
else if ((res->flags & MEM_MASK) == MEM_TYPE)
lim = &limits.mem;
else if ((res->flags & IO_MASK) == IO_TYPE)
lim = &limits.io;
else
continue;
printk_spew("%s2: %s@%02lx limit %08Lx\n", __func__,
dev_path(dev), res->index, res->limit);
printk_spew("\tlim->base %08Lx lim->limit %08Lx\n",
lim->base, lim->limit);
/* Is the resource outside the limits? */
if (lim->base > res->base)
res->base = lim->base;
if (res->limit > lim->limit)
res->limit = lim->limit;
}
} }
#if CONFIG_CONSOLE_VGA == 1 #if CONFIG_CONSOLE_VGA == 1
@ -392,9 +666,9 @@ device_t vga_pri = 0;
static void allocate_vga_resource(void) static void allocate_vga_resource(void)
{ {
#warning "FIXME modify allocate_vga_resource so it is less pci centric!" #warning "FIXME modify allocate_vga_resource so it is less pci centric!"
#warning "This function knows to much about PCI stuff, it should be just a ietrator/visitor." #warning "This function knows too much about PCI stuff, it should be just a iterator/visitor."
/* FIXME handle the VGA pallette snooping */ /* FIXME: Handle the VGA palette snooping. */
struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last; struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last;
struct bus *bus; struct bus *bus;
bus = 0; bus = 0;
@ -403,10 +677,10 @@ static void allocate_vga_resource(void)
vga_first = 0; vga_first = 0;
vga_last = 0; vga_last = 0;
for (dev = all_devices; dev; dev = dev->next) { for (dev = all_devices; dev; dev = dev->next) {
if (!dev->enabled) continue; if (!dev->enabled)
continue;
if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) && if (((dev->class >> 16) == PCI_BASE_CLASS_DISPLAY) &&
((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) ((dev->class >> 8) != PCI_CLASS_DISPLAY_OTHER)) {
{
if (!vga_first) { if (!vga_first) {
if (dev->on_mainboard) { if (dev->on_mainboard) {
vga_onboard = dev; vga_onboard = dev;
@ -421,7 +695,7 @@ static void allocate_vga_resource(void)
} }
} }
/* It isn't safe to enable other VGA cards */ /* It isn't safe to enable other VGA cards. */
dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO); dev->command &= ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
} }
} }
@ -431,26 +705,24 @@ static void allocate_vga_resource(void)
if (!vga) { if (!vga) {
vga = vga_first; vga = vga_first;
} }
#if CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST == 1 #if CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST == 1
if (vga_onboard) // will use on board vga as pri if (vga_onboard) // Will use on board VGA as pri.
#else #else
if (!vga) // will use last add on adapter as pri if (!vga) // Will use last add on adapter as pri.
#endif #endif
{ {
vga = vga_onboard; vga = vga_onboard;
} }
if (vga) { if (vga) {
/* vga is first add on card or the only onboard vga */ /* VGA is first add on card or the only onboard VGA. */
printk_debug("Allocating VGA resource %s\n", dev_path(vga)); printk_debug("Allocating VGA resource %s\n", dev_path(vga));
/* All legacy VGA cards have MEM & I/O space registers */ /* All legacy VGA cards have MEM & I/O space registers. */
vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO); vga->command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
vga_pri = vga; vga_pri = vga;
bus = vga->bus; bus = vga->bus;
} }
/* Now walk up the bridges setting the VGA enable */ /* Now walk up the bridges setting the VGA enable. */
while (bus) { while (bus) {
printk_debug("Setting PCI_BRIDGE_CTL_VGA for bridge %s\n", printk_debug("Setting PCI_BRIDGE_CTL_VGA for bridge %s\n",
dev_path(bus->dev)); dev_path(bus->dev));
@ -461,7 +733,6 @@ static void allocate_vga_resource(void)
#endif #endif
/** /**
* @brief Assign the computed resources to the devices on the bus. * @brief Assign the computed resources to the devices on the bus.
* *
@ -539,8 +810,7 @@ void enable_resources(struct device *dev)
*/ */
int reset_bus(struct bus *bus) int reset_bus(struct bus *bus)
{ {
if (bus && bus->dev && bus->dev->ops && bus->dev->ops->reset_bus) if (bus && bus->dev && bus->dev->ops && bus->dev->ops->reset_bus) {
{
bus->dev->ops->reset_bus(bus); bus->dev->ops->reset_bus(bus);
bus->reset_needed = 0; bus->reset_needed = 0;
return 1; return 1;
@ -551,37 +821,34 @@ int reset_bus(struct bus *bus)
/** /**
* @brief Scan for devices on a bus. * @brief Scan for devices on a bus.
* *
* If there are bridges on the bus, recursively scan the buses behind the bridges. * If there are bridges on the bus, recursively scan the buses behind the
* If the setting up and tuning of the bus causes a reset to be required, * bridges. If the setting up and tuning of the bus causes a reset to be
* reset the bus and scan it again. * required, reset the bus and scan it again.
* *
* @param bus pointer to the bus device * @param busdev Pointer to the bus device.
* @param max current bus number * @param max Current bus number.
* * @return The maximum bus number found, after scanning all subordinate buses.
* @return The maximum bus number found, after scanning all subordinate busses
*/ */
unsigned int scan_bus(device_t bus, unsigned int max) unsigned int scan_bus(struct device *busdev, unsigned int max)
{ {
unsigned int new_max; unsigned int new_max;
int do_scan_bus; int do_scan_bus;
if ( !bus || if (!busdev || !busdev->enabled || !busdev->ops ||
!bus->enabled || !busdev->ops->scan_bus) {
!bus->ops ||
!bus->ops->scan_bus)
{
return max; return max;
} }
do_scan_bus = 1; do_scan_bus = 1;
while (do_scan_bus) { while (do_scan_bus) {
int link; int link;
new_max = bus->ops->scan_bus(bus, max); new_max = busdev->ops->scan_bus(busdev, max);
do_scan_bus = 0; do_scan_bus = 0;
for(link = 0; link < bus->links; link++) { for (link = 0; link < busdev->links; link++) {
if (bus->link[link].reset_needed) { if (busdev->link[link].reset_needed) {
if (reset_bus(&bus->link[link])) { if (reset_bus(&busdev->link[link])) {
do_scan_bus = 1; do_scan_bus = 1;
} else { } else {
bus->bus->reset_needed = 1; busdev->bus->reset_needed = 1;
} }
} }
} }
@ -589,7 +856,6 @@ unsigned int scan_bus(device_t bus, unsigned int max)
return new_max; return new_max;
} }
/** /**
* @brief Determine the existence of devices and extend the device tree. * @brief Determine the existence of devices and extend the device tree.
* *
@ -619,7 +885,7 @@ void dev_enumerate(void)
printk_info("Enumerating buses...\n"); printk_info("Enumerating buses...\n");
root = &dev_root; root = &dev_root;
show_all_devs(BIOS_DEBUG, "Before Phase 3."); show_all_devs(BIOS_DEBUG, "Before Device Enumeration.");
printk_debug("Compare with tree...\n"); printk_debug("Compare with tree...\n");
show_devs_tree(root, BIOS_DEBUG, 0, 0); show_devs_tree(root, BIOS_DEBUG, 0, 0);
@ -643,66 +909,115 @@ void dev_enumerate(void)
* requried by each device. In the second pass, the resources ranges are * requried by each device. In the second pass, the resources ranges are
* relocated to their final position and stored to the hardware. * relocated to their final position and stored to the hardware.
* *
* I/O resources start at DEVICE_IO_START and grow upward. MEM resources start * I/O resources grow upward. MEM resources grow downward.
* at DEVICE_MEM_HIGH and grow downward.
* *
* Since the assignment is hierarchical we set the values into the dev_root * Since the assignment is hierarchical we set the values into the dev_root
* struct. * struct.
*/ */
void dev_configure(void) void dev_configure(void)
{ {
struct resource *io, *mem; struct resource *res;
struct device *root; struct device *root;
struct device *child;
int i;
printk_info("Allocating resources...\n"); printk_info("Allocating resources...\n");
root = &dev_root; root = &dev_root;
print_resource_tree(root, BIOS_DEBUG, "Original."); /* Each domain should create resources which contain the entire address
* space for IO, MEM, and PREFMEM resources in the domain. The
* allocation of device resources will be done from this address space.
*/
if (!root->ops || !root->ops->read_resources) { /* Read the resources for the entire tree. */
printk_err("dev_root missing read_resources\n");
return;
}
if (!root->ops || !root->ops->set_resources) {
printk_err("dev_root missing set_resources\n");
return;
}
printk_info("Reading resources...\n"); printk_info("Reading resources...\n");
root->ops->read_resources(root); read_resources(&root->link[0]);
printk_info("Done reading resources.\n"); printk_info("Done reading resources.\n");
print_resource_tree(root, BIOS_DEBUG, "After reading."); print_resource_tree(root, BIOS_DEBUG, "After reading.");
/* Get the resources */ /* Compute resources for all domains. */
io = &root->resource[0]; for (child = root->link[0].children; child; child = child->sibling) {
mem = &root->resource[1]; if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
/* Make certain the io devices are allocated somewhere safe. */ continue;
io->base = DEVICE_IO_START; for (i = 0; i < child->resources; i++) {
io->flags |= IORESOURCE_ASSIGNED; res = &child->resource[i];
io->flags &= ~IORESOURCE_STORED; if (res->flags & IORESOURCE_FIXED)
/* Now reallocate the pci resources memory with the continue;
* highest addresses I can manage. if (res->flags & IORESOURCE_PREFETCH) {
compute_resources(&child->link[0],
res, MEM_MASK, PREF_TYPE);
continue;
}
if (res->flags & IORESOURCE_MEM) {
compute_resources(&child->link[0],
res, MEM_MASK, MEM_TYPE);
continue;
}
if (res->flags & IORESOURCE_IO) {
compute_resources(&child->link[0],
res, IO_MASK, IO_TYPE);
continue;
}
}
}
/* For all domains. */
for (child = root->link[0].children; child; child=child->sibling)
if (child->path.type == DEVICE_PATH_PCI_DOMAIN)
avoid_fixed_resources(child);
/* Now we need to adjust the resources. MEM resources need to start at
* the highest address managable.
*/ */
mem->base = resource_max(&root->resource[1]); for (child = root->link[0].children; child; child = child->sibling) {
mem->flags |= IORESOURCE_ASSIGNED; if (child->path.type != DEVICE_PATH_PCI_DOMAIN)
mem->flags &= ~IORESOURCE_STORED; continue;
for (i = 0; i < child->resources; i++) {
res = &child->resource[i];
if (!(res->flags & IORESOURCE_MEM) ||
res->flags & IORESOURCE_FIXED)
continue;
res->base = resource_max(res);
}
}
#if CONFIG_CONSOLE_VGA == 1 #if CONFIG_CONSOLE_VGA == 1
/* Allocate the VGA I/O resource.. */ /* Allocate the VGA I/O resource. */
allocate_vga_resource(); allocate_vga_resource();
print_resource_tree(root, BIOS_DEBUG, "After VGA."); print_resource_tree(root, BIOS_DEBUG, "After VGA.");
#endif #endif
/* Store the computed resource allocations into device registers ... */ /* Store the computed resource allocations into device registers ... */
printk_info("Setting resources...\n"); printk_info("Setting resources...\n");
root->ops->set_resources(root); for (child = root->link[0].children; child; child = child->sibling) {
if (!(child->path.type == DEVICE_PATH_PCI_DOMAIN))
continue;
for (i = 0; i < child->resources; i++) {
res = &child->resource[i];
if (res->flags & IORESOURCE_FIXED)
continue;
if (res->flags & IORESOURCE_PREFETCH) {
allocate_resources(&child->link[0],
res, MEM_MASK, PREF_TYPE);
continue;
}
if (res->flags & IORESOURCE_MEM) {
allocate_resources(&child->link[0],
res, MEM_MASK, MEM_TYPE);
continue;
}
if (res->flags & IORESOURCE_IO) {
allocate_resources(&child->link[0],
res, IO_MASK, IO_TYPE);
continue;
}
}
}
assign_resources(&root->link[0]);
printk_info("Done setting resources.\n"); printk_info("Done setting resources.\n");
#if 0
mem->flags |= IORESOURCE_STORED;
report_resource_stored(root, mem, "");
#endif
print_resource_tree(root, BIOS_DEBUG, "After assigning values."); print_resource_tree(root, BIOS_DEBUG, "After assigning values.");
printk_info("Done allocating resources.\n"); printk_info("Done allocating resources.\n");
@ -738,11 +1053,11 @@ void dev_initialize(void)
printk_info("Initializing devices...\n"); printk_info("Initializing devices...\n");
for (dev = all_devices; dev; dev = dev->next) { for (dev = all_devices; dev; dev = dev->next) {
if (dev->enabled && !dev->initialized && if (dev->enabled && !dev->initialized &&
dev->ops && dev->ops->init) dev->ops && dev->ops->init) {
{
if (dev->path.type == DEVICE_PATH_I2C) { if (dev->path.type == DEVICE_PATH_I2C) {
printk_debug("smbus: %s[%d]->", printk_debug("smbus: %s[%d]->",
dev_path(dev->bus->dev), dev->bus->link); dev_path(dev->bus->dev),
dev->bus->link);
} }
printk_debug("%s init\n", dev_path(dev)); printk_debug("%s init\n", dev_path(dev));
dev->initialized = 1; dev->initialized = 1;
@ -752,4 +1067,3 @@ void dev_initialize(void)
printk_info("Devices initialized\n"); printk_info("Devices initialized\n");
show_all_devs(BIOS_DEBUG, "After init."); show_all_devs(BIOS_DEBUG, "After init.");
} }

4
src/devices/device_util.c
View File

@ -487,7 +487,7 @@ void search_bus_resources(struct bus *bus,
for(curdev = bus->children; curdev; curdev = curdev->sibling) { for(curdev = bus->children; curdev; curdev = curdev->sibling) {
int i; int i;
/* Ignore disabled devices */ /* Ignore disabled devices */
if (!curdev->have_resources) continue; if (!curdev->enabled) continue;
for(i = 0; i < curdev->resources; i++) { for(i = 0; i < curdev->resources; i++) {
struct resource *resource = &curdev->resource[i]; struct resource *resource = &curdev->resource[i];
/* If it isn't the right kind of resource ignore it */ /* If it isn't the right kind of resource ignore it */
@ -514,7 +514,7 @@ void search_global_resources(
for(curdev = all_devices; curdev; curdev = curdev->next) { for(curdev = all_devices; curdev; curdev = curdev->next) {
int i; int i;
/* Ignore disabled devices */ /* Ignore disabled devices */
if (!curdev->have_resources) continue; if (!curdev->enabled) continue;
for(i = 0; i < curdev->resources; i++) { for(i = 0; i < curdev->resources; i++) {
struct resource *resource = &curdev->resource[i]; struct resource *resource = &curdev->resource[i];
/* If it isn't the right kind of resource ignore it */ /* If it isn't the right kind of resource ignore it */

644
src/devices/pci_device.c
View File

File diff suppressed because it is too large Load Diff

33
src/devices/root_device.c
View File

@ -34,29 +34,7 @@
*/ */
void root_dev_read_resources(device_t root) void root_dev_read_resources(device_t root)
{ {
struct resource *resource; printk_err("%s should never be called.\n", __func__);
/* Initialize the system wide io space constraints */
resource = new_resource(root, 0);
resource->base = 0x400;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&root->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system wide memory resources constraints */
resource = new_resource(root, 1);
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffffffUL;
resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&root->link[0], resource,
IORESOURCE_MEM, IORESOURCE_MEM);
} }
/** /**
@ -68,14 +46,7 @@ void root_dev_read_resources(device_t root)
*/ */
void root_dev_set_resources(device_t root) void root_dev_set_resources(device_t root)
{ {
struct bus *bus; printk_err("%s should never be called.\n", __func__);
bus = &root->link[0];
compute_allocate_resource(bus,
&root->resource[0], IORESOURCE_IO, IORESOURCE_IO);
compute_allocate_resource(bus,
&root->resource[1], IORESOURCE_MEM, IORESOURCE_MEM);
assign_resources(bus);
} }
/** /**

9
src/include/device/device.h
View File

@ -69,17 +69,16 @@ struct device {
unsigned int hdr_type; /* PCI header type */ unsigned int hdr_type; /* PCI header type */
unsigned int enabled : 1; /* set if we should enable the device */ unsigned int enabled : 1; /* set if we should enable the device */
unsigned int initialized : 1; /* set if we have initialized the device */ unsigned int initialized : 1; /* set if we have initialized the device */
unsigned int have_resources : 1; /* Set if we have read the devices resources */
unsigned int on_mainboard : 1; unsigned int on_mainboard : 1;
unsigned long rom_address; unsigned long rom_address;
uint8_t command; u8 command;
/* Base registers for this device. I/O, MEM and Expansion ROM */ /* Base registers for this device. I/O, MEM and Expansion ROM */
struct resource resource[MAX_RESOURCES]; struct resource resource[MAX_RESOURCES];
unsigned int resources; unsigned int resources;
/* link are (down stream) buses attached to the device, usually a leaf /* links are (downstream) buses attached to the device, usually a leaf
* device with no children have 0 buses attached and a bridge has 1 bus * device with no children have 0 buses attached and a bridge has 1 bus
*/ */
struct bus link[MAX_LINKS]; struct bus link[MAX_LINKS];
@ -106,8 +105,6 @@ void dev_optimize(void);
/* Generic device helper functions */ /* Generic device helper functions */
int reset_bus(struct bus *bus); int reset_bus(struct bus *bus);
unsigned int scan_bus(struct device *bus, unsigned int max); unsigned int scan_bus(struct device *bus, unsigned int max);
void compute_allocate_resource(struct bus *bus, struct resource *bridge,
unsigned long type_mask, unsigned long type);
void assign_resources(struct bus *bus); void assign_resources(struct bus *bus);
void enable_resources(struct device *dev); void enable_resources(struct device *dev);
void enumerate_static_device(void); void enumerate_static_device(void);
@ -142,6 +139,8 @@ void show_all_devs_resources(int debug_level, const char* msg);
#define DEVICE_MEM_ALIGN 4096 #define DEVICE_MEM_ALIGN 4096
extern struct device_operations default_dev_ops_root; extern struct device_operations default_dev_ops_root;
void pci_domain_read_resources(struct device *dev);
unsigned int pci_domain_scan_bus(struct device *dev, unsigned int max);
void root_dev_read_resources(device_t dev); void root_dev_read_resources(device_t dev);
void root_dev_set_resources(device_t dev); void root_dev_set_resources(device_t dev);
unsigned int scan_static_bus(device_t bus, unsigned int max); unsigned int scan_static_bus(device_t bus, unsigned int max);

15
src/include/device/resource.h
View File

@ -1,5 +1,5 @@
#ifndef RESOURCE_H #ifndef DEVICE_RESOURCE_H
#define RESOURCE_H #define DEVICE_RESOURCE_H
#include <stdint.h> #include <stdint.h>
@ -19,6 +19,7 @@
#define IORESOURCE_SUBTRACTIVE 0x00040000 /* This resource filters all of the unclaimed transactions #define IORESOURCE_SUBTRACTIVE 0x00040000 /* This resource filters all of the unclaimed transactions
* to the bus below. * to the bus below.
*/ */
#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */
#define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */ #define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */
#define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */ #define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */
#define IORESOURCE_FIXED 0x80000000 /* An IO resource the allocator must not change */ #define IORESOURCE_FIXED 0x80000000 /* An IO resource the allocator must not change */
@ -62,7 +63,7 @@
#define IORESOURCE_MEM_EXPANSIONROM (1<<6) #define IORESOURCE_MEM_EXPANSIONROM (1<<6)
typedef uint64_t resource_t; typedef u64 resource_t;
struct resource { struct resource {
resource_t base; /* Base address of the resource */ resource_t base; /* Base address of the resource */
resource_t size; /* Size of the resource */ resource_t size; /* Size of the resource */
@ -74,10 +75,14 @@ struct resource {
/* Alignment must be >= the granularity of the resource */ /* Alignment must be >= the granularity of the resource */
}; };
/* Macros to generate index values for subtractive resources */ /* Macros to generate index values for resources */
#define IOINDEX_SUBTRACTIVE(IDX,LINK) (0x10000000 + ((IDX) << 8) + LINK) #define IOINDEX_SUBTRACTIVE(IDX,LINK) (0x10000000 + ((IDX) << 8) + LINK)
#define IOINDEX_SUBTRACTIVE_LINK(IDX) (IDX & 0xff) #define IOINDEX_SUBTRACTIVE_LINK(IDX) (IDX & 0xff)
#define IOINDEX(IDX,LINK) (((LINK) << 16) + IDX)
#define IOINDEX_LINK(IDX) (( IDX & 0xf0000) >> 16)
#define IOINDEX_IDX(IDX) (IDX & 0xffff)
/* Generic resource helper functions */ /* Generic resource helper functions */
struct device; struct device;
struct bus; struct bus;
@ -101,4 +106,4 @@ extern void search_global_resources(
#define RESOURCE_TYPE_MAX 20 #define RESOURCE_TYPE_MAX 20
extern const char *resource_type(struct resource *resource); extern const char *resource_type(struct resource *resource);
#endif /* RESOURCE_H */ #endif /* DEVICE_RESOURCE_H */

58
src/northbridge/amd/amdfam10/northbridge.c
View File

@ -341,7 +341,7 @@ static int reg_useable(u32 reg,device_t goal_dev, u32 goal_nodeid,
if (!dev) if (!dev)
continue; continue;
for(link = 0; !res && (link < 8); link++) { for(link = 0; !res && (link < 8); link++) {
res = probe_resource(dev, 0x1000 + reg + (link<<16)); // 8 links, 0x1000 man f1, res = probe_resource(dev, IOINDEX(0x1000 + reg, link));
} }
} }
result = 2; result = 2;
@ -385,7 +385,7 @@ static struct resource *amdfam10_find_iopair(device_t dev, u32 nodeid, u32 link)
reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255 reg = 0x110+ (index<<24) + (4<<20); // index could be 0, 255
} }
resource = new_resource(dev, 0x1000 + reg + (link<<16)); resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
return resource; return resource;
} }
@ -421,7 +421,7 @@ static struct resource *amdfam10_find_mempair(device_t dev, u32 nodeid, u32 link
reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63 reg = 0x110+ (index<<24) + (6<<20); // index could be 0, 63
} }
resource = new_resource(dev, 0x1000 + reg + (link<<16)); resource = new_resource(dev, IOINDEX(0x1000 + reg, link));
return resource; return resource;
} }
@ -447,8 +447,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = align; resource->gran = align;
resource->limit = 0xffffUL; resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO; resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_IO, IORESOURCE_IO);
} }
/* Initialize the prefetchable memory constraints on the current bus */ /* Initialize the prefetchable memory constraints on the current bus */
@ -460,9 +458,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN); resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL; resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
#if CONFIG_EXT_CONF_SUPPORT == 1 #if CONFIG_EXT_CONF_SUPPORT == 1
if((resource->index & 0x1fff) == 0x1110) { // ext if((resource->index & 0x1fff) == 0x1110) { // ext
@ -481,9 +476,6 @@ static void amdfam10_link_read_bases(device_t dev, u32 nodeid, u32 link)
resource->gran = log2(HT_MEM_HOST_ALIGN); resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL; resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM; resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
#if CONFIG_EXT_CONF_SUPPORT == 1 #if CONFIG_EXT_CONF_SUPPORT == 1
if((resource->index & 0x1fff) == 0x1110) { // ext if((resource->index & 0x1fff) == 0x1110) { // ext
@ -541,19 +533,14 @@ static void amdfam10_set_resource(device_t dev, struct resource *resource,
/* Get the register and link */ /* Get the register and link */
reg = resource->index & 0xfff; // 4k reg = resource->index & 0xfff; // 4k
link = ( resource->index>> 16)& 0x7; // 8 links link = IOINDEX_LINK(resource->index);
if (resource->flags & IORESOURCE_IO) { if (resource->flags & IORESOURCE_IO) {
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_IO, IORESOURCE_IO);
set_io_addr_reg(dev, nodeid, link, reg, rbase>>8, rend>>8); set_io_addr_reg(dev, nodeid, link, reg, rbase>>8, rend>>8);
store_conf_io_addr(nodeid, link, reg, (resource->index >> 24), rbase>>8, rend>>8); store_conf_io_addr(nodeid, link, reg, (resource->index >> 24), rbase>>8, rend>>8);
} }
else if (resource->flags & IORESOURCE_MEM) { else if (resource->flags & IORESOURCE_MEM) {
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
set_mmio_addr_reg(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8] set_mmio_addr_reg(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8, sysconf.nodes) ;// [39:8]
store_conf_mmio_addr(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8); store_conf_mmio_addr(nodeid, link, reg, (resource->index >>24), rbase>>8, rend>>8);
} }
@ -657,7 +644,7 @@ struct chip_operations northbridge_amd_amdfam10_ops = {
.enable_dev = 0, .enable_dev = 0,
}; };
static void pci_domain_read_resources(device_t dev) static void amdfam10_domain_read_resources(device_t dev)
{ {
struct resource *resource; struct resource *resource;
unsigned reg; unsigned reg;
@ -672,20 +659,20 @@ static void pci_domain_read_resources(device_t dev)
/* Is this register allocated? */ /* Is this register allocated? */
if ((base & 3) != 0) { if ((base & 3) != 0) {
unsigned nodeid, link; unsigned nodeid, link;
device_t dev; device_t reg_dev;
if(reg<0xc0) { // mmio if(reg<0xc0) { // mmio
nodeid = (limit & 0xf) + (base&0x30); nodeid = (limit & 0xf) + (base&0x30);
} else { // io } else { // io
nodeid = (limit & 0xf) + ((base>>4)&0x30); nodeid = (limit & 0xf) + ((base>>4)&0x30);
} }
link = (limit >> 4) & 7; link = (limit >> 4) & 7;
dev = __f0_dev[nodeid]; reg_dev = __f0_dev[nodeid];
if (dev) { if (reg_dev) {
/* Reserve the resource */ /* Reserve the resource */
struct resource *resource; struct resource *reg_resource;
resource = new_resource(dev, 0x1000 + reg + (link<<16)); reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, link));
if (resource) { if (reg_resource) {
resource->flags = 1; reg_resource->flags = 1;
} }
} }
} }
@ -711,24 +698,16 @@ static void pci_domain_read_resources(device_t dev)
resource->base = 0x400; resource->base = 0x400;
resource->limit = 0xffffUL; resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO; resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_IO, IORESOURCE_IO);
/* Initialize the system wide prefetchable memory resources constraints */ /* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1|(link<<2)); resource = new_resource(dev, 1|(link<<2));
resource->limit = 0xfcffffffffULL; resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
/* Initialize the system wide memory resources constraints */ /* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2|(link<<2)); resource = new_resource(dev, 2|(link<<2));
resource->limit = 0xfcffffffffULL; resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM; resource->flags = IORESOURCE_MEM;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
} }
#endif #endif
} }
@ -770,10 +749,6 @@ static u32 find_pci_tolm(struct bus *bus, u32 tolm)
return tolm; return tolm;
} }
#if CONFIG_PCI_64BIT_PREF_MEM == 1
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
#endif
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info { struct hw_mem_hole_info {
@ -980,9 +955,6 @@ static void pci_domain_set_resources(device_t dev)
resource->flags |= IORESOURCE_ASSIGNED; resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED; resource->flags &= ~IORESOURCE_STORED;
link = (resource>>2) & 3; link = (resource>>2) & 3;
compute_allocate_resource(&dev->link[link], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED; resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, ""); report_resource_stored(dev, resource, "");
@ -1142,7 +1114,7 @@ static void pci_domain_set_resources(device_t dev)
} }
} }
static u32 pci_domain_scan_bus(device_t dev, u32 max) static u32 amdfam10_domain_scan_bus(device_t dev, u32 max)
{ {
u32 reg; u32 reg;
int i; int i;
@ -1192,11 +1164,11 @@ static u32 pci_domain_scan_bus(device_t dev, u32 max)
} }
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = amdfam10_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,
.scan_bus = pci_domain_scan_bus, .scan_bus = amdfam10_domain_scan_bus,
#if CONFIG_MMCONF_SUPPORT_DEFAULT #if CONFIG_MMCONF_SUPPORT_DEFAULT
.ops_pci_bus = &pci_ops_mmconf, .ops_pci_bus = &pci_ops_mmconf,
#else #else

2
src/northbridge/amd/amdk8/misc_control.c
View File

@ -53,7 +53,7 @@ static void mcf3_read_resources(device_t dev)
if (iommu) { if (iommu) {
/* Add a Gart apeture resource */ /* Add a Gart apeture resource */
resource = new_resource(dev, 0x94); resource = new_resource(dev, 0x94);
resource->size = iommu?CONFIG_AGP_APERTURE_SIZE:1; resource->size = CONFIG_AGP_APERTURE_SIZE;
resource->align = log2(resource->size); resource->align = log2(resource->size);
resource->gran = log2(resource->size); resource->gran = log2(resource->size);
resource->limit = 0xffffffff; /* 4G */ resource->limit = 0xffffffff; /* 4G */

95
src/northbridge/amd/amdk8/northbridge.c
View File

@ -297,7 +297,7 @@ static int reg_useable(unsigned reg,
if (!dev) if (!dev)
continue; continue;
for(link = 0; !res && (link < 3); link++) { for(link = 0; !res && (link < 3); link++) {
res = probe_resource(dev, 0x100 + (reg | link)); res = probe_resource(dev, IOINDEX(0x100 + reg, link));
} }
} }
result = 2; result = 2;
@ -335,7 +335,7 @@ static struct resource *amdk8_find_iopair(device_t dev, unsigned nodeid, unsigne
reg = free_reg; reg = free_reg;
} }
if (reg > 0) { if (reg > 0) {
resource = new_resource(dev, 0x100 + (reg | link)); resource = new_resource(dev, IOINDEX(0x100 + reg, link));
} }
return resource; return resource;
} }
@ -362,7 +362,7 @@ static struct resource *amdk8_find_mempair(device_t dev, unsigned nodeid, unsign
reg = free_reg; reg = free_reg;
} }
if (reg > 0) { if (reg > 0) {
resource = new_resource(dev, 0x100 + (reg | link)); resource = new_resource(dev, IOINDEX(0x100 + reg, link));
} }
return resource; return resource;
} }
@ -379,9 +379,7 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
resource->align = log2(HT_IO_HOST_ALIGN); resource->align = log2(HT_IO_HOST_ALIGN);
resource->gran = log2(HT_IO_HOST_ALIGN); resource->gran = log2(HT_IO_HOST_ALIGN);
resource->limit = 0xffffUL; resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO; resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_IO, IORESOURCE_IO);
} }
/* Initialize the prefetchable memory constraints on the current bus */ /* Initialize the prefetchable memory constraints on the current bus */
@ -393,9 +391,9 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
resource->gran = log2(HT_MEM_HOST_ALIGN); resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL; resource->limit = 0xffffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[link], resource, #ifdef CONFIG_PCI_64BIT_PREF_MEM
IORESOURCE_MEM | IORESOURCE_PREFETCH, resource->flags |= IORESOURCE_BRIDGE;
IORESOURCE_MEM | IORESOURCE_PREFETCH); #endif
} }
/* Initialize the memory constraints on the current bus */ /* Initialize the memory constraints on the current bus */
@ -405,11 +403,8 @@ static void amdk8_link_read_bases(device_t dev, unsigned nodeid, unsigned link)
resource->size = 0; resource->size = 0;
resource->align = log2(HT_MEM_HOST_ALIGN); resource->align = log2(HT_MEM_HOST_ALIGN);
resource->gran = log2(HT_MEM_HOST_ALIGN); resource->gran = log2(HT_MEM_HOST_ALIGN);
resource->limit = 0xffffffffffULL; resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM; resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
} }
} }
@ -432,11 +427,15 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
/* Make certain the resource has actually been set */ /* Make certain the resource has actually been set */
if (!(resource->flags & IORESOURCE_ASSIGNED)) { if (!(resource->flags & IORESOURCE_ASSIGNED)) {
printk_err("%s: can't set unassigned resource @%lx %lx\n",
__func__, resource->index, resource->flags);
return; return;
} }
/* If I have already stored this resource don't worry about it */ /* If I have already stored this resource don't worry about it */
if (resource->flags & IORESOURCE_STORED) { if (resource->flags & IORESOURCE_STORED) {
printk_err("%s: can't set stored resource @%lx %lx\n", __func__,
resource->index, resource->flags);
return; return;
} }
@ -448,6 +447,10 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
if (resource->index < 0x100) { if (resource->index < 0x100) {
return; return;
} }
if (resource->size == 0)
return;
/* Get the base address */ /* Get the base address */
rbase = resource->base; rbase = resource->base;
@ -456,12 +459,10 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
/* Get the register and link */ /* Get the register and link */
reg = resource->index & 0xfc; reg = resource->index & 0xfc;
link = resource->index & 3; link = IOINDEX_LINK(resource->index);
if (resource->flags & IORESOURCE_IO) { if (resource->flags & IORESOURCE_IO) {
uint32_t base, limit; uint32_t base, limit;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_IO, IORESOURCE_IO);
base = f1_read_config32(reg); base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4); limit = f1_read_config32(reg + 0x4);
base &= 0xfe000fcc; base &= 0xfe000fcc;
@ -486,9 +487,6 @@ static void amdk8_set_resource(device_t dev, struct resource *resource, unsigned
} }
else if (resource->flags & IORESOURCE_MEM) { else if (resource->flags & IORESOURCE_MEM) {
uint32_t base, limit; uint32_t base, limit;
compute_allocate_resource(&dev->link[link], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
resource->flags & (IORESOURCE_MEM | IORESOURCE_PREFETCH));
base = f1_read_config32(reg); base = f1_read_config32(reg);
limit = f1_read_config32(reg + 0x4); limit = f1_read_config32(reg + 0x4);
base &= 0x000000f0; base &= 0x000000f0;
@ -634,7 +632,7 @@ struct chip_operations northbridge_amd_amdk8_ops = {
.enable_dev = 0, .enable_dev = 0,
}; };
static void pci_domain_read_resources(device_t dev) static void amdk8_domain_read_resources(device_t dev)
{ {
struct resource *resource; struct resource *resource;
unsigned reg; unsigned reg;
@ -655,48 +653,21 @@ static void pci_domain_read_resources(device_t dev)
if (reg_dev) { if (reg_dev) {
/* Reserve the resource */ /* Reserve the resource */
struct resource *reg_resource; struct resource *reg_resource;
reg_resource = new_resource(reg_dev, 0x100 + (reg | link)); reg_resource = new_resource(reg_dev, IOINDEX(0x100 + reg, link));
if (reg_resource) { if (reg_resource) {
reg_resource->flags = 1; reg_resource->flags = 1;
} }
} }
} }
} }
#if CONFIG_PCI_64BIT_PREF_MEM == 0
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */ pci_domain_read_resources(dev);
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
#else
/* Initialize the system wide io space constraints */
resource = new_resource(dev, 0);
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_IO, IORESOURCE_IO);
#if CONFIG_PCI_64BIT_PREF_MEM == 1
/* Initialize the system wide prefetchable memory resources constraints */ /* Initialize the system wide prefetchable memory resources constraints */
resource = new_resource(dev, 1);
resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM | IORESOURCE_PREFETCH);
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, 2); resource = new_resource(dev, 2);
resource->limit = 0xfcffffffffULL; resource->limit = 0xfcffffffffULL;
resource->flags = IORESOURCE_MEM; resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
compute_allocate_resource(&dev->link[0], resource,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
#endif #endif
} }
@ -739,10 +710,6 @@ static uint32_t find_pci_tolm(struct bus *bus)
return tolm; return tolm;
} }
#if CONFIG_PCI_64BIT_PREF_MEM == 1
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
#endif
#if CONFIG_HW_MEM_HOLE_SIZEK != 0 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info { struct hw_mem_hole_info {
@ -898,7 +865,7 @@ static uint32_t hoist_memory(unsigned long hole_startk, int i)
extern uint64_t high_tables_base, high_tables_size; extern uint64_t high_tables_base, high_tables_size;
#endif #endif
static void pci_domain_set_resources(device_t dev) static void amdk8_domain_set_resources(device_t dev)
{ {
#if CONFIG_PCI_64BIT_PREF_MEM == 1 #if CONFIG_PCI_64BIT_PREF_MEM == 1
struct resource *io, *mem1, *mem2; struct resource *io, *mem1, *mem2;
@ -964,13 +931,7 @@ static void pci_domain_set_resources(device_t dev)
last = &dev->resource[dev->resources]; last = &dev->resource[dev->resources];
for(resource = &dev->resource[0]; resource < last; resource++) for(resource = &dev->resource[0]; resource < last; resource++)
{ {
#if 1
resource->flags |= IORESOURCE_ASSIGNED; resource->flags |= IORESOURCE_ASSIGNED;
resource->flags &= ~IORESOURCE_STORED;
#endif
compute_allocate_resource(&dev->link[0], resource,
BRIDGE_IO_MASK, resource->flags & BRIDGE_IO_MASK);
resource->flags |= IORESOURCE_STORED; resource->flags |= IORESOURCE_STORED;
report_resource_stored(dev, resource, ""); report_resource_stored(dev, resource, "");
@ -1125,7 +1086,7 @@ static void pci_domain_set_resources(device_t dev)
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) static unsigned int amdk8_domain_scan_bus(device_t dev, unsigned int max)
{ {
unsigned reg; unsigned reg;
int i; int i;
@ -1160,11 +1121,11 @@ static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
} }
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = amdk8_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = amdk8_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,
.scan_bus = pci_domain_scan_bus, .scan_bus = amdk8_domain_scan_bus,
.ops_pci_bus = &pci_cf8_conf1, .ops_pci_bus = &pci_cf8_conf1,
}; };

27
src/northbridge/amd/gx1/northbridge.c
View File

@ -66,27 +66,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER, .device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -187,12 +166,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

25
src/northbridge/amd/gx2/northbridge.c
View File

@ -356,25 +356,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_NS_GX2, .device = PCI_DEVICE_ID_NS_GX2,
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __func__);
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -468,12 +449,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

28
src/northbridge/amd/lx/northbridge.c
View File

@ -74,8 +74,6 @@
#define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}} #define IOD_BM(msr, pdid1, bizarro, ibase, imask) {msr, {.hi=(pdid1<<29)|(bizarro<<28)|(ibase>>12), .lo=(ibase<<20)|imask}}
#define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}} #define IOD_SC(msr, pdid1, bizarro, en, wen, ren, ibase) {msr, {.hi=(pdid1<<29)|(bizarro<<28), .lo=(en<<24)|(wen<<21)|(ren<<20)|(ibase<<3)}}
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
extern void graphics_init(void); extern void graphics_init(void);
extern void cpubug(void); extern void cpubug(void);
extern void chipsetinit(void); extern void chipsetinit(void);
@ -382,24 +380,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = PCI_DEVICE_ID_AMD_LXBRIDGE, .device = PCI_DEVICE_ID_AMD_LXBRIDGE,
}; };
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
printk_spew(">> Entering northbridge.c: %s\n", __func__);
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags =
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags =
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -470,14 +450,6 @@ static void pci_domain_enable(device_t dev)
pci_set_method(dev); pci_set_method(dev);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
printk_spew(">> Entering northbridge.c: %s\n", __func__);
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

24
src/northbridge/ibm/cpc710/cpc710_northbridge.c
View File

@ -9,23 +9,6 @@
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include "chip.h" #include "chip.h"
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->base = 0x80000000ULL;
resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -53,13 +36,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

24
src/northbridge/ibm/cpc925/cpc925_northbridge.c
View File

@ -9,23 +9,6 @@
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include "chip.h" #include "chip.h"
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->base = 0x80000000ULL;
resource->limit = 0xfeffffffULL; /* We can put pci resources in the system controll area */
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -53,13 +36,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

23
src/northbridge/intel/e7501/northbridge.c
View File

@ -9,23 +9,6 @@
#include <bitops.h> #include <bitops.h>
#include "chip.h" #include "chip.h"
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
unsigned reg;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400; //yhlu
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -155,12 +138,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

35
src/northbridge/intel/e7520/northbridge.c
View File

@ -28,30 +28,6 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
} }
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffffffUL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new) static void tolm_test(void *gp, struct device *dev, struct resource *new)
{ {
struct resource **best_p = gp; struct resource **best_p = gp;
@ -178,13 +154,10 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) static u32 e7520_domain_scan_bus(device_t dev, u32 max)
{ {
max = pci_scan_bus(&dev->link[0], 0, 0xff, max); max_bus = pci_domain_scan_bus(dev, max);
if (max > max_bus) { return max_bus;
max_bus = max;
}
return max;
} }
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
@ -192,7 +165,7 @@ static struct device_operations pci_domain_ops = {
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,
.scan_bus = pci_domain_scan_bus, .scan_bus = e7520_domain_scan_bus,
.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
}; };

37
src/northbridge/intel/e7525/northbridge.c
View File

@ -28,30 +28,6 @@ static void ram_resource(device_t dev, unsigned long index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
} }
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffffffUL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new) static void tolm_test(void *gp, struct device *dev, struct resource *new)
{ {
struct resource **best_p = gp; struct resource **best_p = gp;
@ -160,7 +136,7 @@ static void pci_domain_set_resources(device_t dev)
/* Report the memory regions */ /* Report the memory regions */
ram_resource(dev, 3, 0, 640); ram_resource(dev, 3, 0, 640);
ram_resource(dev, 4, 768, tolmk - 768); ram_resource(dev, 4, 768, (tolmk - 768));
if (tomk > 4*1024*1024) { if (tomk > 4*1024*1024) {
ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024); ram_resource(dev, 5, 4096*1024, tomk - 4*1024*1024);
} }
@ -178,13 +154,10 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) static u32 e7525_domain_scan_bus(device_t dev, u32 max)
{ {
max = pci_scan_bus(&dev->link[0], 0, 0xff, max); max_bus = pci_domain_scan_bus(dev, max);
if (max > max_bus) { return max_bus;
max_bus = max;
}
return max;
} }
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
@ -192,7 +165,7 @@ static struct device_operations pci_domain_ops = {
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,
.scan_bus = pci_domain_scan_bus, .scan_bus = e7525_domain_scan_bus,
.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
}; };

35
src/northbridge/intel/i3100/northbridge.c
View File

@ -49,30 +49,6 @@ static void ram_resource(device_t dev, u32 index,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
} }
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffffffUL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new) static void tolm_test(void *gp, struct device *dev, struct resource *new)
{ {
struct resource **best_p = gp; struct resource **best_p = gp;
@ -199,13 +175,10 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static u32 pci_domain_scan_bus(device_t dev, u32 max) static u32 i3100_domain_scan_bus(device_t dev, u32 max)
{ {
max = pci_scan_bus(&dev->link[0], 0, 0xff, max); max_bus = pci_domain_scan_bus(dev, max);
if (max > max_bus) { return max_bus;
max_bus = max;
}
return max;
} }
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
@ -213,7 +186,7 @@ static struct device_operations pci_domain_ops = {
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,
.scan_bus = pci_domain_scan_bus, .scan_bus = i3100_domain_scan_bus,
.ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */ .ops_pci_bus = &pci_cf8_conf1, /* Do we want to use the memory mapped space here? */
}; };

28
src/northbridge/intel/i440bx/northbridge.c
View File

@ -33,24 +33,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x7190, .device = 0x7190,
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -95,7 +77,7 @@ static uint32_t find_pci_tolm(struct bus *bus)
extern uint64_t high_tables_base, high_tables_size; extern uint64_t high_tables_base, high_tables_size;
#endif #endif
static void pci_domain_set_resources(device_t dev) static void i440bx_domain_set_resources(device_t dev)
{ {
device_t mc_dev; device_t mc_dev;
uint32_t pci_tolm; uint32_t pci_tolm;
@ -140,15 +122,9 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = i440bx_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,
.scan_bus = pci_domain_scan_bus, .scan_bus = pci_domain_scan_bus,

27
src/northbridge/intel/i82810/northbridge.c
View File

@ -52,27 +52,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x7120, .device = 0x7120,
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
unsigned reg;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags =
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags =
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -181,12 +160,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

25
src/northbridge/intel/i82830/northbridge.c
View File

@ -51,25 +51,6 @@ static struct pci_driver northbridge_driver __pci_driver = {
.device = 0x3575, .device = 0x3575,
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags =
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags =
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -158,12 +139,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

24
src/northbridge/intel/i855gme/northbridge.c
View File

@ -31,24 +31,6 @@
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include "chip.h" #include "chip.h"
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
unsigned reg;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -156,12 +138,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

23
src/northbridge/intel/i855pm/northbridge.c
View File

@ -10,23 +10,6 @@
#include <bitops.h> #include <bitops.h>
#include "chip.h" #include "chip.h"
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -123,12 +106,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

32
src/northbridge/intel/i945/northbridge.c
View File

@ -43,31 +43,6 @@ static void ram_resource(device_t dev, unsigned long index, unsigned long basek,
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
} }
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffUL;
resource->flags =
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->base = 0;
resource->size = 0;
resource->align = 0;
resource->gran = 0;
resource->limit = 0xffffffffUL;
resource->flags =
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new) static void tolm_test(void *gp, struct device *dev, struct resource *new)
{ {
struct resource **best_p = gp; struct resource **best_p = gp;
@ -184,15 +159,10 @@ static void pci_domain_set_resources(device_t dev)
#endif #endif
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], 0, 0xff, max);
/* TODO We could determine how many PCIe busses we need in /* TODO We could determine how many PCIe busses we need in
* the bar. For now that number is hardcoded to a max of 64. * the bar. For now that number is hardcoded to a max of 64.
* See e7525/northbridge.c for an example.
*/ */
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

11
src/northbridge/motorola/mpc107/mpc107_northbridge.c
View File

@ -16,7 +16,7 @@
* be large enough to hold all expected resources for all PCI * be large enough to hold all expected resources for all PCI
* devices. * devices.
*/ */
static void pci_domain_read_resources(device_t dev) static void mpc107_domain_read_resources(device_t dev)
{ {
struct resource *resource; struct resource *resource;
@ -101,15 +101,8 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = mpc107_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,

22
src/northbridge/via/cn400/northbridge.c
View File

@ -101,11 +101,11 @@ static const struct pci_driver memctrl_driver __pci_driver = {
.device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL, .device = PCI_DEVICE_ID_VIA_CN400_MEMCTRL,
}; };
static void pci_domain_read_resources(device_t dev) static void cn400_domain_read_resources(device_t dev)
{ {
struct resource *resource; struct resource *resource;
printk_spew("Entering cn400 pci_domain_read_resources.\n"); printk_spew("Entering %s.\n", __func__);
/* Initialize the system wide I/O space constraints. */ /* Initialize the system wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
@ -119,7 +119,7 @@ static void pci_domain_read_resources(device_t dev)
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED; IORESOURCE_ASSIGNED;
printk_spew("Leaving cn400 pci_domain_read_resources.\n"); printk_spew("Leaving %s.\n", __func__);
} }
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
@ -173,14 +173,14 @@ static u32 find_pci_tolm(struct bus *bus)
extern uint64_t high_tables_base, high_tables_size; extern uint64_t high_tables_base, high_tables_size;
#endif #endif
static void pci_domain_set_resources(device_t dev) static void cn400_domain_set_resources(device_t dev)
{ {
/* The order is important to find the correct RAM size. */ /* The order is important to find the correct RAM size. */
static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; static const u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 };
device_t mc_dev; device_t mc_dev;
u32 pci_tolm; u32 pci_tolm;
printk_spew("Entering cn400 pci_domain_set_resources.\n"); printk_spew("Entering %s.\n", __func__);
pci_tolm = find_pci_tolm(&dev->link[0]); pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev_find_device(PCI_VENDOR_ID_VIA, mc_dev = dev_find_device(PCI_VENDOR_ID_VIA,
@ -226,23 +226,23 @@ static void pci_domain_set_resources(device_t dev)
} }
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
printk_spew("Leaving cn400 pci_domain_set_resources.\n"); printk_spew("Leaving %s.\n", __func__);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max) static unsigned int cn400_domain_scan_bus(device_t dev, unsigned int max)
{ {
printk_debug("Entering cn400 pci_domain_scan_bus.\n"); printk_debug("Entering %s.\n", __func__);
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max); max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max; return max;
} }
static const struct device_operations pci_domain_ops = { static const struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = cn400_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = cn400_domain_set_resources,
.enable_resources = enable_childrens_resources, .enable_resources = enable_childrens_resources,
.init = 0, .init = 0,
.scan_bus = pci_domain_scan_bus, .scan_bus = cn400_domain_scan_bus,
}; };
static void cpu_bus_init(device_t dev) static void cpu_bus_init(device_t dev)

29
src/northbridge/via/cn700/northbridge.c
View File

@ -97,27 +97,6 @@ static const struct pci_driver memctrl_driver __pci_driver = {
.device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL, .device = PCI_DEVICE_ID_VIA_CN700_MEMCTRL,
}; };
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
printk_spew("Entering cn700 pci_domain_read_resources.\n");
/* Initialize the system wide I/O space constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints. */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
printk_spew("Leaving cn700 pci_domain_read_resources.\n");
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -223,14 +202,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
printk_debug("Entering cn700 pci_domain_scan_bus.\n");
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static const struct device_operations pci_domain_ops = { static const struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

17
src/northbridge/via/cx700/cx700_lpc.c
View File

@ -329,7 +329,7 @@ static void cx700_set_lpc_registers(struct device *dev)
void cx700_read_resources(device_t dev) void cx700_read_resources(device_t dev)
{ {
struct resource *resource; struct resource *res;
/* Make sure we call our childrens set/enable functions - these /* Make sure we call our childrens set/enable functions - these
* are not called unless this device has a resource to set. * are not called unless this device has a resource to set.
@ -337,11 +337,16 @@ void cx700_read_resources(device_t dev)
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
resource = new_resource(dev, 1); res = new_resource(dev, 1);
resource->flags |= res->base = 0x0UL;
IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED; res->size = 0x400UL;
resource->size = 2; res->limit = 0xffffUL;
resource->base = 0x2e; res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
void cx700_set_resources(device_t dev) void cx700_set_resources(device_t dev)

21
src/northbridge/via/cx700/northbridge.c
View File

@ -32,21 +32,6 @@
#include "chip.h" #include "chip.h"
#include "northbridge.h" #include "northbridge.h"
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -146,12 +131,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

23
src/northbridge/via/vt8601/northbridge.c
View File

@ -45,23 +45,6 @@ static const struct pci_driver northbridge_driver __pci_driver = {
.device = 0x0601, /* 0x8601 is the AGP bridge? */ .device = 0x0601, /* 0x8601 is the AGP bridge? */
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -160,12 +143,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

32
src/northbridge/via/vt8623/northbridge.c
View File

@ -190,30 +190,6 @@ static const struct pci_driver vga_driver __pci_driver = {
.device = 0x3122, .device = 0x3122,
}; };
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
printk_spew("Entering vt8623 pci_domain_read_resources.\n");
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
printk_spew("Leaving vt8623 pci_domain_read_resources.\n");
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -313,14 +289,6 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
printk_spew("Entering vt8623 pci_domain_scan_bus.\n");
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = { static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

29
src/northbridge/via/vx800/northbridge.c
View File

@ -69,27 +69,6 @@ static const struct pci_driver memctrl_driver __pci_driver = {
.device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL, .device = PCI_DEVICE_ID_VIA_VX855_MEMCTRL,
}; };
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
printk_spew("Entering vx800 pci_domain_read_resources.\n");
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED;
printk_spew("Leaving vx800 pci_domain_read_resources.\n");
}
static void ram_resource(device_t dev, unsigned long index, static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek) unsigned long basek, unsigned long sizek)
{ {
@ -195,14 +174,6 @@ if register with invalid value we set frame buffer size to 32M for default, but
assign_resources(&dev->link[0]); assign_resources(&dev->link[0]);
} }
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
printk_debug("Entering vx800 pci_domain_scan_bus.\n");
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static const struct device_operations pci_domain_ops = { static const struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources, .read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources, .set_resources = pci_domain_set_resources,

19
src/southbridge/amd/amd8111/amd8111_lpc.c
View File

@ -162,15 +162,26 @@ static void amd8111_lpc_read_resources(device_t dev)
{ {
struct resource *res; struct resource *res;
/* Get the normal pci resources of this device */ /* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void amd8111_lpc_enable_resources(device_t dev) static void amd8111_lpc_enable_resources(device_t dev)

3
src/southbridge/amd/amd8131/amd8131_bridge.c
View File

@ -364,9 +364,6 @@ static void bridge_set_resources(struct device *dev)
/* set the memory range */ /* set the memory range */
dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
res->flags |= IORESOURCE_STORED; res->flags |= IORESOURCE_STORED;
compute_allocate_resource(&dev->link[0], res,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
base = res->base; base = res->base;
end = resource_end(res); end = resource_end(res);
pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);

3
src/southbridge/amd/amd8132/amd8132_bridge.c
View File

@ -350,9 +350,6 @@ static void bridge_set_resources(struct device *dev)
/* set the memory range */ /* set the memory range */
dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; dev->command |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
res->flags |= IORESOURCE_STORED; res->flags |= IORESOURCE_STORED;
compute_allocate_resource(&dev->link[0], res,
IORESOURCE_MEM | IORESOURCE_PREFETCH,
IORESOURCE_MEM);
base = res->base; base = res->base;
end = resource_end(res); end = resource_end(res);
pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16); pci_write_config16(dev, PCI_MEMORY_BASE, base >> 16);

20
src/southbridge/amd/cs5530/cs5530_isa.c
View File

@ -25,6 +25,24 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include "cs5530.h" #include "cs5530.h"
static void cs5530_read_resources(device_t dev)
{
struct resource* res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x400UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void isa_init(struct device *dev) static void isa_init(struct device *dev)
{ {
uint8_t reg8; uint8_t reg8;
@ -45,7 +63,7 @@ static void cs5530_pci_dev_enable_resources(device_t dev)
} }
static struct device_operations isa_ops = { static struct device_operations isa_ops = {
.read_resources = pci_dev_read_resources, .read_resources = cs5530_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = cs5530_pci_dev_enable_resources, .enable_resources = cs5530_pci_dev_enable_resources,
.init = isa_init, .init = isa_init,

20
src/southbridge/amd/cs5535/cs5535.c
View File

@ -69,6 +69,24 @@ static void southbridge_enable(struct device *dev)
printk_spew("%s: dev is %p\n", __func__, dev); printk_spew("%s: dev is %p\n", __func__, dev);
} }
static void cs5535_read_resources(device_t dev)
{
struct resource* res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x400UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void cs5535_pci_dev_enable_resources(device_t dev) static void cs5535_pci_dev_enable_resources(device_t dev)
{ {
printk_spew("cs5535.c: %s()\n", __func__); printk_spew("cs5535.c: %s()\n", __func__);
@ -77,7 +95,7 @@ static void cs5535_pci_dev_enable_resources(device_t dev)
} }
static struct device_operations southbridge_ops = { static struct device_operations southbridge_ops = {
.read_resources = pci_dev_read_resources, .read_resources = cs5535_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = cs5535_pci_dev_enable_resources, .enable_resources = cs5535_pci_dev_enable_resources,
.init = southbridge_init, .init = southbridge_init,

21
src/southbridge/amd/cs5536/cs5536.c
View File

@ -607,6 +607,25 @@ static void southbridge_init(struct device *dev)
} }
} }
static void cs5536_read_resources(device_t dev)
{
struct resource *res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x400UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void southbridge_enable(struct device *dev) static void southbridge_enable(struct device *dev)
{ {
printk_err("cs5536: %s: dev is %p\n", __func__, dev); printk_err("cs5536: %s: dev is %p\n", __func__, dev);
@ -621,7 +640,7 @@ static void cs5536_pci_dev_enable_resources(device_t dev)
} }
static struct device_operations southbridge_ops = { static struct device_operations southbridge_ops = {
.read_resources = pci_dev_read_resources, .read_resources = cs5536_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = cs5536_pci_dev_enable_resources, .enable_resources = cs5536_pci_dev_enable_resources,
.init = southbridge_init, .init = southbridge_init,

21
src/southbridge/amd/sb600/sb600_lpc.c
View File

@ -70,14 +70,23 @@ static void sb600_lpc_read_resources(device_t dev)
pci_get_resource(dev, 0xA0); /* SPI ROM base address */ pci_get_resource(dev, 0xA0); /* SPI ROM base address */
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = res->base = 0;
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = res->base = 0xff800000;
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
compact_resources(dev); compact_resources(dev);
} }
@ -111,7 +120,7 @@ static void sb600_lpc_enable_childrens_resources(device_t dev)
for (child = dev->link[link].children; child; for (child = dev->link[link].children; child;
child = child->sibling) { child = child->sibling) {
enable_resources(child); enable_resources(child);
if (child->have_resources if (child->enabled
&& (child->path.type == DEVICE_PATH_PNP)) { && (child->path.type == DEVICE_PATH_PNP)) {
for (i = 0; i < child->resources; i++) { for (i = 0; i < child->resources; i++) {
struct resource *res; struct resource *res;

19
src/southbridge/broadcom/bcm5785/bcm5785_lpc.c
View File

@ -29,18 +29,27 @@ static void lpc_init(device_t dev)
static void bcm5785_lpc_read_resources(device_t dev) static void bcm5785_lpc_read_resources(device_t dev)
{ {
struct resource *res; struct resource *res;
unsigned long index;
/* Get the normal pci resources of this device */ /* Get the normal pci resources of this device */
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
/** /**
@ -69,7 +78,7 @@ static void bcm5785_lpc_enable_childrens_resources(device_t dev)
device_t child; device_t child;
for (child = dev->link[link].children; child; child = child->sibling) { for (child = dev->link[link].children; child; child = child->sibling) {
enable_resources(child); enable_resources(child);
if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
for(i=0;i<child->resources;i++) { for(i=0;i<child->resources;i++) {
struct resource *res; struct resource *res;
unsigned long base, end; // don't need long long unsigned long base, end; // don't need long long

1
src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
View File

@ -51,7 +51,6 @@ static void bcm5785_sb_read_resources(device_t dev)
/* Get the normal pci resources of this device */ /* Get the normal pci resources of this device */
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* Get Resource for SMBUS */ /* Get Resource for SMBUS */
pci_get_resource(dev, 0x90); pci_get_resource(dev, 0x90);

17
src/southbridge/intel/esb6300/esb6300_lpc.c
View File

@ -361,12 +361,23 @@ static void esb6300_lpc_read_resources(device_t dev)
/* Add the GPIO BAR */ /* Add the GPIO BAR */
res = pci_get_resource(dev, GPIO_BAR); res = pci_get_resource(dev, GPIO_BAR);
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void esb6300_lpc_enable_resources(device_t dev) static void esb6300_lpc_enable_resources(device_t dev)

17
src/southbridge/intel/i3100/i3100_lpc.c
View File

@ -399,12 +399,23 @@ static void i3100_lpc_read_resources(device_t dev)
/* Add the GPIO BAR */ /* Add the GPIO BAR */
res = pci_get_resource(dev, GPIO_BAR); res = pci_get_resource(dev, GPIO_BAR);
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* Add resource for RCBA */ /* Add resource for RCBA */
res = new_resource(dev, RCBA); res = new_resource(dev, RCBA);

27
src/southbridge/intel/i82371eb/i82371eb_isa.c
View File

@ -55,8 +55,31 @@ static void isa_init(struct device *dev)
isa_dma_init(); isa_dma_init();
} }
static const struct device_operations isa_ops = { static void sb_read_resources(struct device *dev)
.read_resources = pci_dev_read_resources, {
struct resource *res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x1000UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 2);
res->base = 0xff800000UL;
res->size = 0x00800000UL; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
const struct device_operations isa_ops = {
.read_resources = sb_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = isa_init, .init = isa_init,

19
src/southbridge/intel/i82801ca/i82801ca_lpc.c
View File

@ -207,15 +207,26 @@ static void i82801ca_lpc_read_resources(device_t dev)
{ {
struct resource *res; struct resource *res;
/* Get the normal pci resources of this device */ /* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void i82801ca_lpc_enable_resources(device_t dev) static void i82801ca_lpc_enable_resources(device_t dev)

19
src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
View File

@ -182,15 +182,26 @@ static void i82801dbm_lpc_read_resources(device_t dev)
{ {
struct resource *res; struct resource *res;
/* Get the normal pci resources of this device */ /* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void i82801dbm_lpc_enable_resources(device_t dev) static void i82801dbm_lpc_enable_resources(device_t dev)

19
src/southbridge/intel/i82801er/i82801er_lpc.c
View File

@ -334,7 +334,7 @@ static void i82801er_lpc_read_resources(device_t dev)
{ {
struct resource *res; struct resource *res;
/* Get the normal pci resources of this device */ /* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
/* Add the ACPI BAR */ /* Add the ACPI BAR */
@ -343,12 +343,23 @@ static void i82801er_lpc_read_resources(device_t dev)
/* Add the GPIO BAR */ /* Add the GPIO BAR */
res = pci_get_resource(dev, GPIO_BAR); res = pci_get_resource(dev, GPIO_BAR);
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void i82801er_lpc_enable_resources(device_t dev) static void i82801er_lpc_enable_resources(device_t dev)

17
src/southbridge/intel/i82801gx/i82801gx_lpc.c
View File

@ -419,12 +419,21 @@ static void i82801gx_lpc_read_resources(device_t dev)
/* Add an extra subtractive resource for both memory and I/O. */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = res->base = 0;
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = res->base = 0xff800000;
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void i82801gx_lpc_enable_resources(device_t dev) static void i82801gx_lpc_enable_resources(device_t dev)

17
src/southbridge/intel/i82801xx/i82801xx_lpc.c
View File

@ -340,12 +340,21 @@ static void i82801xx_lpc_read_resources(device_t dev)
/* Add an extra subtractive resource for both memory and I/O. */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = res->base = 0;
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = res->base = 0xff800000;
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
static void i82801xx_lpc_enable_resources(device_t dev) static void i82801xx_lpc_enable_resources(device_t dev)

19
src/southbridge/nvidia/ck804/ck804_lpc.c
View File

@ -275,12 +275,21 @@ static void ck804_lpc_read_resources(device_t dev)
/* Add an extra subtractive resource for both memory and I/O. */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = res->base = 0;
IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = res->base = 0xff800000;
IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
/** /**
@ -308,7 +317,7 @@ static void ck804_lpc_enable_childrens_resources(device_t dev)
device_t child; device_t child;
for (child = dev->link[link].children; child; child = child->sibling) { for (child = dev->link[link].children; child; child = child->sibling) {
enable_resources(child); enable_resources(child);
if (child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { if (child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
for (i = 0; i < child->resources; i++) { for (i = 0; i < child->resources; i++) {
struct resource *res; struct resource *res;
unsigned long base, end; // don't need long long unsigned long base, end; // don't need long long

30
src/southbridge/nvidia/ck804/ck804_pci.c
View File

@ -5,6 +5,7 @@
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/resource.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@ -13,10 +14,8 @@
static void pci_init(struct device *dev) static void pci_init(struct device *dev)
{ {
uint32_t dword; uint32_t dword;
#if CONFIG_PCI_64BIT_PREF_MEM == 1
device_t pci_domain_dev; device_t pci_domain_dev;
struct resource *mem1, *mem2; struct resource *mem, *pref;
#endif
dword = pci_read_config32(dev, 0x04); dword = pci_read_config32(dev, 0x04);
dword |= (1 << 8); /* System error enable */ dword |= (1 << 8); /* System error enable */
@ -36,7 +35,6 @@ static void pci_init(struct device *dev)
pci_write_config32(dev, 0x4c, dword); pci_write_config32(dev, 0x4c, dword);
#endif #endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1
pci_domain_dev = dev->bus->dev; pci_domain_dev = dev->bus->dev;
while (pci_domain_dev) { while (pci_domain_dev) {
if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
@ -47,21 +45,19 @@ static void pci_init(struct device *dev)
if (!pci_domain_dev) if (!pci_domain_dev)
return; /* Impossible */ return; /* Impossible */
mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
mem2 = find_resource(pci_domain_dev, 2); // mem mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
if (mem1->base > mem2->base) {
dword = mem2->base & (0xffff0000UL); if (!mem)
printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base); return; /* Impossible */
if (!pref || pref->base > mem->base) {
dword = mem->base & (0xffff0000UL);
printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
} else { } else {
dword = mem1->base & (0xffff0000UL); dword = pref->base & (0xffff0000UL);
printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
mem1->base);
} }
#else
dword = dev_root.resource[1].base & (0xffff0000UL);
printk_debug("dev_root mem base = 0x%010Lx\n",
dev_root.resource[1].base);
#endif
printk_debug("[0x50] <-- 0x%08x\n", dword); printk_debug("[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); /* TOM */ pci_write_config32(dev, 0x50, dword); /* TOM */

25
src/southbridge/nvidia/mcp55/mcp55_lpc.c
View File

@ -248,16 +248,27 @@ static void mcp55_lpc_read_resources(device_t dev)
{ {
struct resource *res; struct resource *res;
/* Get the normal pci resources of this device */ /* Get the normal PCI resources of this device. */
pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP /* We got one for APIC, or one more for TRAP. */
pci_dev_read_resources(dev);
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
/** /**
@ -265,7 +276,7 @@ static void mcp55_lpc_read_resources(device_t dev)
* *
* @param dev the device whos children's resources are to be enabled * @param dev the device whos children's resources are to be enabled
* *
* This function is call by the global enable_resources() indirectly via the * This function is called by the global enable_resources() indirectly via the
* device_operation::enable_resources() method of devices. * device_operation::enable_resources() method of devices.
* *
* Indirect mutual recursion: * Indirect mutual recursion:
@ -286,7 +297,7 @@ static void mcp55_lpc_enable_childrens_resources(device_t dev)
device_t child; device_t child;
for (child = dev->link[link].children; child; child = child->sibling) { for (child = dev->link[link].children; child; child = child->sibling) {
enable_resources(child); enable_resources(child);
if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
for(i=0;i<child->resources;i++) { for(i=0;i<child->resources;i++) {
struct resource *res; struct resource *res;
unsigned long base, end; // don't need long long unsigned long base, end; // don't need long long

43
src/southbridge/nvidia/mcp55/mcp55_pci.c
View File

@ -23,6 +23,7 @@
#include <console/console.h> #include <console/console.h>
#include <device/device.h> #include <device/device.h>
#include <device/resource.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <device/pci_ops.h> #include <device/pci_ops.h>
@ -33,10 +34,8 @@ static void pci_init(struct device *dev)
uint32_t dword; uint32_t dword;
uint16_t word; uint16_t word;
#if CONFIG_PCI_64BIT_PREF_MEM == 1
device_t pci_domain_dev; device_t pci_domain_dev;
struct resource *mem1, *mem2; struct resource *mem, *pref;
#endif
/* System error enable */ /* System error enable */
dword = pci_read_config32(dev, 0x04); dword = pci_read_config32(dev, 0x04);
@ -58,30 +57,32 @@ static void pci_init(struct device *dev)
pci_write_config32(dev, 0x4c, dword); pci_write_config32(dev, 0x4c, dword);
#endif #endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1
pci_domain_dev = dev->bus->dev; pci_domain_dev = dev->bus->dev;
while (pci_domain_dev) { while (pci_domain_dev) {
if(pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN) break; if (pci_domain_dev->path.type == DEVICE_PATH_PCI_DOMAIN)
break;
pci_domain_dev = pci_domain_dev->bus->dev; pci_domain_dev = pci_domain_dev->bus->dev;
} }
if(!pci_domain_dev) return; // impossiable if (!pci_domain_dev)
mem1 = find_resource(pci_domain_dev, 1); // prefmem, it could be 64bit return; /* Impossible */
mem2 = find_resource(pci_domain_dev, 2); // mem
if(mem1->base > mem2->base) {
dword = mem2->base & (0xffff0000UL);
printk_debug("PCI DOMAIN mem2 base = 0x%010Lx\n", mem2->base);
} else {
dword = mem1->base & (0xffff0000UL);
printk_debug("PCI DOMAIN mem1 (prefmem) base = 0x%010Lx\n", mem1->base);
}
#else
dword = dev_root.resource[1].base & (0xffff0000UL);
printk_debug("dev_root mem base = 0x%010Lx\n", dev_root.resource[1].base);
#endif
printk_debug("[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); //TOM
pref = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(2,0));
mem = probe_resource(pci_domain_dev, IOINDEX_SUBTRACTIVE(1,0));
if (!mem)
return; /* Impossible */
if (!pref || pref->base > mem->base) {
dword = mem->base & (0xffff0000UL);
printk_debug("PCI DOMAIN mem base = 0x%010Lx\n", mem->base);
} else {
dword = pref->base & (0xffff0000UL);
printk_debug("PCI DOMAIN pref base = 0x%010Lx\n", pref->base);
}
printk_debug("[0x50] <-- 0x%08x\n", dword);
pci_write_config32(dev, 0x50, dword); /* TOM */
} }
static struct pci_operations lops_pci = { static struct pci_operations lops_pci = {

1
src/southbridge/ricoh/rl5c476/rl5c476.c
View File

@ -172,7 +172,6 @@ void rl5c476_set_resources(device_t dev)
resource = find_resource(dev,1); resource = find_resource(dev,1);
if( !(resource->flags & IORESOURCE_STORED) ){ if( !(resource->flags & IORESOURCE_STORED) ){
resource->flags |= IORESOURCE_STORED ; resource->flags |= IORESOURCE_STORED ;
compute_allocate_resource(&dev->link[0],resource,resource->flags,resource->flags);
printk_debug("%s 1 ==> %x\n",dev_path(dev),resource->base); printk_debug("%s 1 ==> %x\n",dev_path(dev),resource->base);
cf_base = resource->base; cf_base = resource->base;
} }

18
src/southbridge/sis/sis966/sis966_lpc.c
View File

@ -239,13 +239,23 @@ static void sis966_lpc_read_resources(device_t dev)
/* Get the normal pci resources of this device */ /* Get the normal pci resources of this device */
pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP pci_dev_read_resources(dev); // We got one for APIC, or one more for TRAP
/* Add an extra subtractive resource for both memory and I/O */ /* Add an extra subtractive resource for both memory and I/O. */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0;
res->size = 0x1000;
res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; res->base = 0xff800000;
res->size = 0x00800000; /* 8 MB for flash */
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
/** /**
@ -274,7 +284,7 @@ static void sis966_lpc_enable_childrens_resources(device_t dev)
device_t child; device_t child;
for (child = dev->link[link].children; child; child = child->sibling) { for (child = dev->link[link].children; child; child = child->sibling) {
enable_resources(child); enable_resources(child);
if(child->have_resources && (child->path.type == DEVICE_PATH_PNP)) { if(child->enabled && (child->path.type == DEVICE_PATH_PNP)) {
for(i=0;i<child->resources;i++) { for(i=0;i<child->resources;i++) {
struct resource *res; struct resource *res;
unsigned long base, end; // don't need long long unsigned long base, end; // don't need long long

20
src/southbridge/via/vt8231/vt8231_lpc.c
View File

@ -131,6 +131,24 @@ static void vt8231_init(struct device *dev)
rtc_init(0); rtc_init(0);
} }
void vt8231_read_resources(device_t dev)
{
struct resource *res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x400UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static void southbridge_init(struct device *dev) static void southbridge_init(struct device *dev)
{ {
vt8231_init(dev); vt8231_init(dev);
@ -138,7 +156,7 @@ static void southbridge_init(struct device *dev)
} }
static struct device_operations vt8231_lpc_ops = { static struct device_operations vt8231_lpc_ops = {
.read_resources = pci_dev_read_resources, .read_resources = vt8231_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources, .enable_resources = pci_dev_enable_resources,
.init = &southbridge_init, .init = &southbridge_init,

17
src/southbridge/via/vt8235/vt8235_lpc.c
View File

@ -219,15 +219,22 @@ static void vt8235_init(struct device *dev)
device has a resource to set - so set a dummy one */ device has a resource to set - so set a dummy one */
void vt8235_read_resources(device_t dev) void vt8235_read_resources(device_t dev)
{ {
struct resource *res;
struct resource *resource;
pci_dev_read_resources(dev); pci_dev_read_resources(dev);
resource = new_resource(dev, 1);
resource->flags |= IORESOURCE_FIXED | IORESOURCE_ASSIGNED | IORESOURCE_IO | IORESOURCE_STORED;
resource->size = 2;
resource->base = 0x2e;
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x400UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
} }
void vt8235_set_resources(device_t dev) void vt8235_set_resources(device_t dev)
{ {
struct resource *resource; struct resource *resource;

20
src/southbridge/winbond/w83c553/w83c553f.c
View File

@ -188,8 +188,26 @@ static void w83c553_enable_resources(device_t dev)
enable_childrens_resources(dev); enable_childrens_resources(dev);
} }
static void w83c553_read_resources(device_t dev)
{
struct resource* res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x400UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = 0xfec00000;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static struct device_operations w83c553_ops = { static struct device_operations w83c553_ops = {
.read_resources = pci_dev_read_resources, .read_resources = w83c553_read_resources,
.set_resources = pci_dev_set_resources, .set_resources = pci_dev_set_resources,
.enable_resources = w83c553_enable_resources, .enable_resources = w83c553_enable_resources,
.init = w83c553_init, .init = w83c553_init,