lenovo/t430s: Add new port.
The port is based on the x230 / t530. Tested - is in active use. Change-Id: Ic5ccfe70343e8aef3465690edce9cdebf153a44d Signed-off-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-on: http://review.coreboot.org/8359 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This commit is contained in:
Nicolas Reinecke
Alexandru Gagniuc
parent
b5669ba579
commit
29d358e6a1
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@ -37,6 +37,11 @@ config BOARD_LENOVO_T420S
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help
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Lenovo T420s laptop. Consult wiki for details.
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config BOARD_LENOVO_T430S
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bool "ThinkPad T430s"
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help
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Lenovo T430s laptop. Consult wiki for details.
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config BOARD_LENOVO_T520
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bool "ThinkPad T520"
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help
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@ -68,6 +73,7 @@ source "src/mainboard/lenovo/x201/Kconfig"
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source "src/mainboard/lenovo/x220/Kconfig"
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source "src/mainboard/lenovo/x230/Kconfig"
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source "src/mainboard/lenovo/t420s/Kconfig"
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source "src/mainboard/lenovo/t430s/Kconfig"
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source "src/mainboard/lenovo/t520/Kconfig"
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source "src/mainboard/lenovo/t530/Kconfig"
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source "src/mainboard/lenovo/t60/Kconfig"
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@ -0,0 +1,72 @@
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if BOARD_LENOVO_T430S
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select CPU_INTEL_SOCKET_RPGA989
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select NORTHBRIDGE_INTEL_IVYBRIDGE_NATIVE
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select SOUTHBRIDGE_INTEL_C216
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select EC_LENOVO_PMH7
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select EC_LENOVO_H8
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select NO_UART_ON_SUPERIO
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select BOARD_ROMSIZE_KB_16384
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select HAVE_ACPI_TABLES
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select HAVE_OPTION_TABLE
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select HAVE_CMOS_DEFAULT
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select HAVE_ACPI_RESUME
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select INTEL_INT15
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select VGA
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select INTEL_EDID
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select MAINBOARD_HAS_NATIVE_VGA_INIT
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select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
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select IVYBRIDGE_LVDS
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select ENABLE_VMX
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# Workaround for EC/KBC IRQ1.
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select SERIRQ_CONTINUOUS_MODE
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config HAVE_IFD_BIN
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bool
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default n
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config HAVE_ME_BIN
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bool
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default n
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config MAINBOARD_DIR
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string
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default lenovo/t430s
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config MAINBOARD_PART_NUMBER
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string
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default "ThinkPad T430s"
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config MMCONF_BASE_ADDRESS
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hex
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default 0xf0000000
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config MAX_CPUS
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int
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default 8
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config USBDEBUG_HCD_INDEX
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int
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default 2
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config DRAM_RESET_GATE_GPIO
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int
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default 10
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config VGA_BIOS_FILE
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string
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default "pci8086,0166.rom"
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config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
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hex
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default 0x17aa
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config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
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hex
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default 0x21fb
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endif # BOARD_LENOVO_T430S
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@ -0,0 +1,21 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
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romstage-y += gpio.c
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (c) 2011 Sven Schnelle <svens@stackframe.org>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
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* MA 02110-1301 USA
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*/
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#include <ec/lenovo/h8/acpi/ec.asl>
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Scope(\_SB.PCI0.LPCB.EC)
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{
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}
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@ -0,0 +1,77 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011-2012 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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/* The APM port can be used for generating software SMIs */
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OperationRegion (APMP, SystemIO, 0xb2, 2)
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Field (APMP, ByteAcc, NoLock, Preserve)
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{
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APMC, 8, // APM command
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APMS, 8 // APM status
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}
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/* Port 80 POST */
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OperationRegion (POST, SystemIO, 0x80, 1)
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Field (POST, ByteAcc, Lock, Preserve)
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{
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DBG0, 8
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}
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/* SMI I/O Trap */
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Method(TRAP, 1, Serialized)
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{
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Store (Arg0, SMIF) // SMI Function
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Store (0, TRP0) // Generate trap
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Return (SMIF) // Return value of SMI handler
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}
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/* The _PIC method is called by the OS to choose between interrupt
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* routing via the i8259 interrupt controller or the APIC.
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*
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* _PIC is called with a parameter of 0 for i8259 configuration and
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* with a parameter of 1 for Local Apic/IOAPIC configuration.
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*/
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Method(_PIC, 1)
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{
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// Remember the OS' IRQ routing choice.
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Store(Arg0, PICM)
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}
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/* The _PTS method (Prepare To Sleep) is called before the OS is
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* entering a sleep state. The sleep state number is passed in Arg0
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*/
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Method(_PTS,1)
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{
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}
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/* The _WAK method is called on system wakeup */
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Method(_WAK,1)
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{
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/* ME may not be up yet. */
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Store (0, \_TZ.MEB1)
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Store (0, \_TZ.MEB2)
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/* Not implemented. */
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Return(Package(){0,0})
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}
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@ -0,0 +1 @@
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#include <drivers/pc80/ps2_controller.asl>
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@ -0,0 +1,64 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2009 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/acpigen.h>
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#include <southbridge/intel/bd82x6x/nvs.h>
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#include "thermal.h"
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static void acpi_update_thermal_table(global_nvs_t *gnvs)
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{
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gnvs->tcrt = CRITICAL_TEMPERATURE;
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gnvs->tpsv = PASSIVE_TEMPERATURE;
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}
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void acpi_create_gnvs(global_nvs_t *gnvs)
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{
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/* Disable USB ports in S3 by default */
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gnvs->s3u0 = 0;
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gnvs->s3u1 = 0;
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/* Disable USB ports in S5 by default */
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gnvs->s5u0 = 0;
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gnvs->s5u1 = 0;
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/* IGD Displays */
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gnvs->ndid = 3;
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gnvs->did[0] = 0x80000100;
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gnvs->did[1] = 0x80000240;
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gnvs->did[2] = 0x80000410;
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gnvs->did[3] = 0x80000410;
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gnvs->did[4] = 0x00000005;
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// the lid is open by default.
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gnvs->lids = 1;
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acpi_update_thermal_table(gnvs);
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}
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unsigned long acpi_fill_slit(unsigned long current)
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{
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// Not implemented
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return current;
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}
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unsigned long acpi_fill_srat(unsigned long current)
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{
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/* No NUMA, no SRAT */
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return current;
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}
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@ -0,0 +1,5 @@
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Category: laptop
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ROM package: SOIC-8 / WSON-8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: n
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@ -0,0 +1,18 @@
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boot_option=Fallback
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last_boot=Fallback
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baud_rate=115200
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debug_level=Spew
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power_on_after_fail=Enable
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nmi=Enable
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volume=0x3
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first_battery=Primary
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bluetooth=Enable
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wwan=Enable
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wlan=Enable
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touchpad=Enable
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sata_mode=AHCI
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fn_ctrl_swap=Disable
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sticky_fn=Disable
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trackpoint=Enable
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hyper_threading=Enable
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backlight=Both
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@ -0,0 +1,167 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2007-2008 coresystems GmbH
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## Copyright (C) 2014 Vladimir Serbinenko
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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# -----------------------------------------------------------------
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entries
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#start-bit length config config-ID name
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#0 8 r 0 seconds
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#8 8 r 0 alarm_seconds
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#16 8 r 0 minutes
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#24 8 r 0 alarm_minutes
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#32 8 r 0 hours
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#40 8 r 0 alarm_hours
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#48 8 r 0 day_of_week
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#56 8 r 0 day_of_month
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#64 8 r 0 month
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#72 8 r 0 year
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# -----------------------------------------------------------------
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# Status Register A
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#80 4 r 0 rate_select
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#84 3 r 0 REF_Clock
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#87 1 r 0 UIP
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# -----------------------------------------------------------------
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# Status Register B
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#88 1 r 0 auto_switch_DST
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#89 1 r 0 24_hour_mode
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#90 1 r 0 binary_values_enable
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#91 1 r 0 square-wave_out_enable
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#92 1 r 0 update_finished_enable
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#93 1 r 0 alarm_interrupt_enable
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#94 1 r 0 periodic_interrupt_enable
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#95 1 r 0 disable_clock_updates
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# -----------------------------------------------------------------
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# Status Register C
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#96 4 r 0 status_c_rsvd
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#100 1 r 0 uf_flag
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#101 1 r 0 af_flag
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#102 1 r 0 pf_flag
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#103 1 r 0 irqf_flag
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# -----------------------------------------------------------------
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# Status Register D
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#104 7 r 0 status_d_rsvd
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#111 1 r 0 valid_cmos_ram
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# -----------------------------------------------------------------
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# Diagnostic Status Register
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#112 8 r 0 diag_rsvd1
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# -----------------------------------------------------------------
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0 120 r 0 reserved_memory
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#120 264 r 0 unused
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# -----------------------------------------------------------------
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# RTC_BOOT_BYTE (coreboot hardcoded)
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384 1 e 4 boot_option
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385 1 e 4 last_boot
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388 4 r 0 reboot_bits
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#390 2 r 0 unused?
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# -----------------------------------------------------------------
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# coreboot config options: console
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392 3 e 5 baud_rate
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395 4 e 6 debug_level
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#399 1 r 0 unused
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400 8 h 0 volume
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# coreboot config options: southbridge
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408 1 e 1 nmi
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409 2 e 7 power_on_after_fail
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# coreboot config options: EC
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411 1 e 8 first_battery
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412 1 e 1 bluetooth
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413 1 e 1 wwan
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414 1 e 1 touchpad
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415 1 e 1 wlan
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416 1 e 1 trackpoint
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417 1 e 1 fn_ctrl_swap
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418 1 e 1 sticky_fn
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#419 2 r 0 unused
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421 1 e 9 sata_mode
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422 2 e 10 backlight
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# coreboot config options: cpu
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424 1 e 2 hyper_threading
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#425 7 r 0 unused
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# coreboot config options: northbridge
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432 3 e 11 gfx_uma_size
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#435 549 r 0 unused
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# SandyBridge MRC Scrambler Seed values
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896 32 r 0 mrc_scrambler_seed
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928 32 r 0 mrc_scrambler_seed_s3
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960 16 r 0 mrc_scrambler_seed_chk
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# coreboot config options: check sums
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984 16 h 0 check_sum
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# -----------------------------------------------------------------
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enumerations
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#ID value text
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1 0 Disable
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1 1 Enable
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2 0 Enable
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2 1 Disable
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4 0 Fallback
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4 1 Normal
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5 0 115200
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5 1 57600
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5 2 38400
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5 3 19200
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5 4 9600
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5 5 4800
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5 6 2400
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5 7 1200
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6 1 Emergency
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6 2 Alert
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6 3 Critical
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6 4 Error
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6 5 Warning
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6 6 Notice
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6 7 Info
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6 8 Debug
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6 9 Spew
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7 0 Disable
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7 1 Enable
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7 2 Keep
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8 0 Secondary
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8 1 Primary
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9 0 AHCI
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9 1 Compatible
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10 0 Both
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10 1 Keyboard only
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10 2 Thinklight only
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10 3 None
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11 0 32M
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11 1 64M
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||||
11 2 96M
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11 3 128M
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11 4 160M
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11 5 192M
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||||
11 6 224M
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||||
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||||
# -----------------------------------------------------------------
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checksums
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checksum 392 415 984
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@ -0,0 +1,172 @@
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chip northbridge/intel/sandybridge
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# Enable DisplayPort Hotplug with 6ms pulse
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register "gpu_dp_d_hotplug" = "0x06"
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|
||||
# Enable Panel as LVDS and configure power delays
|
||||
register "gpu_panel_port_select" = "0" # LVDS
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||||
register "gpu_panel_power_cycle_delay" = "6" # T7: 500ms
|
||||
register "gpu_panel_power_up_delay" = "100" # T1+T2: 10ms
|
||||
register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
|
||||
register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
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||||
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
|
||||
register "gfx.use_spread_spectrum_clock" = "1"
|
||||
register "gfx.lvds_dual_channel" = "1"
|
||||
register "gfx.link_frequency_270_mhz" = "1"
|
||||
register "gfx.lvds_num_lanes" = "1"
|
||||
register "gpu_cpu_backlight" = "0x1155"
|
||||
register "gpu_pch_backlight" = "0x11551155"
|
||||
|
||||
device cpu_cluster 0 on
|
||||
chip cpu/intel/socket_rPGA989
|
||||
device lapic 0 on end
|
||||
end
|
||||
chip cpu/intel/model_206ax
|
||||
# Magic APIC ID to locate this chip
|
||||
device lapic 0xACAC off end
|
||||
|
||||
# Coordinate with HW_ALL
|
||||
register "pstate_coord_type" = "0xfe"
|
||||
|
||||
register "c1_acpower" = "1" # ACPI(C1) = MWAIT(C1)
|
||||
register "c2_acpower" = "3" # ACPI(C2) = MWAIT(C3)
|
||||
register "c3_acpower" = "5" # ACPI(C3) = MWAIT(C7)
|
||||
|
||||
register "c1_battery" = "1" # ACPI(C1) = MWAIT(C1)
|
||||
register "c2_battery" = "3" # ACPI(C2) = MWAIT(C3)
|
||||
register "c3_battery" = "5" # ACPI(C3) = MWAIT(C7)
|
||||
end
|
||||
end
|
||||
|
||||
device domain 0 on
|
||||
device pci 00.0 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # host bridge
|
||||
device pci 01.0 off end # PCIe Bridge for discrete graphics
|
||||
device pci 02.0 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # Integrated Graphics Controller
|
||||
|
||||
chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH
|
||||
# GPI routing
|
||||
# 0 No effect (default)
|
||||
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)
|
||||
# 2 SCI (if corresponding GPIO_EN bit is also set)
|
||||
register "alt_gp_smi_en" = "0x0000"
|
||||
register "gpi1_routing" = "2"
|
||||
register "gpi13_routing" = "2"
|
||||
|
||||
# Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock)
|
||||
register "sata_port_map" = "0x17"
|
||||
# Set max SATA speed to 6.0 Gb/s
|
||||
register "sata_interface_speed_support" = "0x3"
|
||||
|
||||
register "gen1_dec" = "0x7c1601"
|
||||
register "gen2_dec" = "0x0c15e1"
|
||||
register "gen4_dec" = "0x0c06a1"
|
||||
|
||||
register "pcie_hotplug_map" = "{ 0, 0, 1, 0, 0, 0, 0, 0 }"
|
||||
|
||||
# Enable zero-based linear PCIe root port functions
|
||||
register "pcie_port_coalesce" = "1"
|
||||
register "c2_latency" = "101" # c2 not supported
|
||||
register "p_cnt_throttling_supported" = "1"
|
||||
|
||||
device pci 14.0 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # USB 3.0 Controller
|
||||
device pci 16.0 off end # Management Engine Interface 1
|
||||
device pci 16.1 off end # Management Engine Interface 2
|
||||
device pci 16.2 off end # Management Engine IDE-R
|
||||
device pci 16.3 off end # Management Engine KT
|
||||
device pci 19.0 on
|
||||
subsystemid 0x17aa 0x21f3
|
||||
end # Intel Gigabit Ethernet
|
||||
device pci 1a.0 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # USB Enhanced Host Controller #2
|
||||
device pci 1b.0 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # High Definition Audio Controller
|
||||
device pci 1c.0 off end # PCIe Port #1
|
||||
device pci 1c.1 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # PCIe Port #2 Integrated Wireless LAN
|
||||
device pci 1c.2 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # PCIe Port #3 ExpressCard
|
||||
device pci 1c.3 off end # PCIe Port #4
|
||||
device pci 1c.4 off end # PCIe Port #5
|
||||
device pci 1c.5 off end # PCIe Port #6 Intel Gigabit Ethernet PHY (not PCIe)
|
||||
device pci 1c.6 off end # PCIe Port #7
|
||||
device pci 1c.7 off end # PCIe Port #8
|
||||
device pci 1d.0 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # USB Enhanced Host Controller #1
|
||||
device pci 1e.0 off end # PCI bridge
|
||||
device pci 1f.0 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
chip ec/lenovo/pmh7
|
||||
device pnp ff.1 on # dummy
|
||||
end
|
||||
register "backlight_enable" = "0x01"
|
||||
register "dock_event_enable" = "0x01"
|
||||
end
|
||||
|
||||
chip ec/lenovo/h8
|
||||
device pnp ff.2 on # dummy
|
||||
io 0x60 = 0x62
|
||||
io 0x62 = 0x66
|
||||
io 0x64 = 0x1600
|
||||
io 0x66 = 0x1604
|
||||
end
|
||||
|
||||
register "config0" = "0xa7"
|
||||
register "config1" = "0x05"
|
||||
register "config2" = "0xa0"
|
||||
register "config3" = "0xe2"
|
||||
|
||||
register "has_keyboard_backlight" = "1"
|
||||
|
||||
register "beepmask0" = "0x00"
|
||||
register "beepmask1" = "0x86"
|
||||
register "has_power_management_beeps" = "0"
|
||||
register "event2_enable" = "0xff"
|
||||
register "event3_enable" = "0xff"
|
||||
register "event4_enable" = "0xd0"
|
||||
register "event5_enable" = "0x3c"
|
||||
register "event6_enable" = "0x00"
|
||||
register "event7_enable" = "0x01"
|
||||
register "event8_enable" = "0x7b"
|
||||
register "event9_enable" = "0xff"
|
||||
register "eventa_enable" = "0x00"
|
||||
register "eventb_enable" = "0x00"
|
||||
register "eventc_enable" = "0xff"
|
||||
register "eventd_enable" = "0xff"
|
||||
register "evente_enable" = "0x0d"
|
||||
end
|
||||
end # LPC Controller
|
||||
device pci 1f.2 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # 6 port SATA AHCI Controller
|
||||
device pci 1f.3 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
# eeprom, 8 virtual devices, same chip
|
||||
chip drivers/i2c/at24rf08c
|
||||
device i2c 54 on end
|
||||
device i2c 55 on end
|
||||
device i2c 56 on end
|
||||
device i2c 57 on end
|
||||
device i2c 5c on end
|
||||
device i2c 5d on end
|
||||
device i2c 5e on end
|
||||
device i2c 5f on end
|
||||
end
|
||||
end # SMBus Controller
|
||||
device pci 1f.5 off end # SATA Controller 2
|
||||
device pci 1f.6 on
|
||||
subsystemid 0x17aa 0x21fb
|
||||
end # Thermal
|
||||
end
|
||||
end
|
||||
end
|
||||
|
|
@ -0,0 +1,56 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#define THINKPAD_EC_GPE 17
|
||||
#define BRIGHTNESS_UP \_SB.PCI0.GFX0.LCD0.INCB
|
||||
#define BRIGHTNESS_DOWN \_SB.PCI0.GFX0.LCD0.DECB
|
||||
#define ACPI_VIDEO_DEVICE \_SB.PCI0.GFX0
|
||||
#define EC_LENOVO_H8_ME_WORKAROUND 1
|
||||
#define HAVE_LCD_SCREEN 1
|
||||
|
||||
DefinitionBlock(
|
||||
"dsdt.aml",
|
||||
"DSDT",
|
||||
0x02, // DSDT revision: ACPI v2.0
|
||||
"COREv4", // OEM id
|
||||
"COREBOOT", // OEM table id
|
||||
0x20110725 // OEM revision
|
||||
)
|
||||
{
|
||||
// Some generic macros
|
||||
#include "acpi/platform.asl"
|
||||
|
||||
// global NVS and variables
|
||||
#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
|
||||
|
||||
#include <cpu/intel/model_206ax/acpi/cpu.asl>
|
||||
|
||||
Scope (\_SB) {
|
||||
Device (PCI0)
|
||||
{
|
||||
#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
|
||||
#include <southbridge/intel/bd82x6x/acpi/pch.asl>
|
||||
}
|
||||
}
|
||||
|
||||
/* Chipset specific sleep states */
|
||||
#include <southbridge/intel/bd82x6x/acpi/sleepstates.asl>
|
||||
}
|
||||
|
|
@ -0,0 +1,290 @@
|
|||
#include "southbridge/intel/bd82x6x/gpio.h"
|
||||
const struct pch_gpio_set1 pch_gpio_set1_mode = {
|
||||
.gpio0 = GPIO_MODE_GPIO,
|
||||
.gpio1 = GPIO_MODE_GPIO, // -EC_SCI - input
|
||||
.gpio2 = GPIO_MODE_GPIO,
|
||||
.gpio3 = GPIO_MODE_GPIO,
|
||||
.gpio4 = GPIO_MODE_GPIO,
|
||||
.gpio5 = GPIO_MODE_GPIO,
|
||||
.gpio6 = GPIO_MODE_GPIO,
|
||||
.gpio7 = GPIO_MODE_GPIO,
|
||||
.gpio8 = GPIO_MODE_GPIO,
|
||||
.gpio9 = GPIO_MODE_NATIVE, // OC5 - -USB_PORT9_OC5 - input
|
||||
.gpio10 = GPIO_MODE_GPIO, // DRAMRST_GATE_ON - output
|
||||
.gpio11 = GPIO_MODE_NATIVE,
|
||||
.gpio12 = GPIO_MODE_NATIVE,
|
||||
.gpio13 = GPIO_MODE_GPIO, // -EC_WAKE - input
|
||||
.gpio14 = GPIO_MODE_NATIVE,
|
||||
.gpio15 = GPIO_MODE_GPIO,
|
||||
.gpio16 = GPIO_MODE_NATIVE,
|
||||
.gpio17 = GPIO_MODE_GPIO,
|
||||
.gpio18 = GPIO_MODE_NATIVE,
|
||||
.gpio19 = GPIO_MODE_NATIVE,
|
||||
.gpio20 = GPIO_MODE_NATIVE,
|
||||
.gpio21 = GPIO_MODE_GPIO,
|
||||
.gpio22 = GPIO_MODE_GPIO,
|
||||
.gpio23 = GPIO_MODE_NATIVE,
|
||||
.gpio24 = GPIO_MODE_GPIO,
|
||||
.gpio25 = GPIO_MODE_NATIVE,
|
||||
.gpio26 = GPIO_MODE_NATIVE,
|
||||
.gpio27 = GPIO_MODE_GPIO,
|
||||
.gpio28 = GPIO_MODE_GPIO,
|
||||
.gpio29 = GPIO_MODE_GPIO,
|
||||
.gpio30 = GPIO_MODE_NATIVE,
|
||||
.gpio31 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_direction = {
|
||||
.gpio0 = GPIO_DIR_INPUT,
|
||||
.gpio1 = GPIO_DIR_INPUT,
|
||||
.gpio2 = GPIO_DIR_INPUT,
|
||||
.gpio3 = GPIO_DIR_INPUT,
|
||||
.gpio4 = GPIO_DIR_INPUT,
|
||||
.gpio5 = GPIO_DIR_INPUT,
|
||||
.gpio6 = GPIO_DIR_INPUT,
|
||||
.gpio7 = GPIO_DIR_INPUT,
|
||||
.gpio8 = GPIO_DIR_OUTPUT,
|
||||
.gpio9 = GPIO_DIR_INPUT,
|
||||
.gpio10 = GPIO_DIR_OUTPUT,
|
||||
.gpio11 = GPIO_DIR_INPUT,
|
||||
.gpio12 = GPIO_DIR_OUTPUT,
|
||||
.gpio13 = GPIO_DIR_INPUT,
|
||||
.gpio14 = GPIO_DIR_INPUT,
|
||||
.gpio15 = GPIO_DIR_OUTPUT,
|
||||
.gpio16 = GPIO_DIR_INPUT,
|
||||
.gpio17 = GPIO_DIR_INPUT,
|
||||
.gpio18 = GPIO_DIR_INPUT,
|
||||
.gpio19 = GPIO_DIR_INPUT,
|
||||
.gpio20 = GPIO_DIR_INPUT,
|
||||
.gpio21 = GPIO_DIR_INPUT,
|
||||
.gpio22 = GPIO_DIR_OUTPUT,
|
||||
.gpio23 = GPIO_DIR_INPUT,
|
||||
.gpio24 = GPIO_DIR_OUTPUT,
|
||||
.gpio25 = GPIO_DIR_INPUT,
|
||||
.gpio26 = GPIO_DIR_INPUT,
|
||||
.gpio27 = GPIO_DIR_OUTPUT,
|
||||
.gpio28 = GPIO_DIR_OUTPUT,
|
||||
.gpio29 = GPIO_DIR_OUTPUT,
|
||||
.gpio30 = GPIO_DIR_OUTPUT,
|
||||
.gpio31 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_level = {
|
||||
.gpio0 = GPIO_LEVEL_LOW,
|
||||
.gpio1 = GPIO_LEVEL_HIGH,
|
||||
.gpio2 = GPIO_LEVEL_LOW,
|
||||
.gpio3 = GPIO_LEVEL_HIGH,
|
||||
.gpio4 = GPIO_LEVEL_HIGH,
|
||||
.gpio5 = GPIO_LEVEL_HIGH,
|
||||
.gpio6 = GPIO_LEVEL_HIGH,
|
||||
.gpio7 = GPIO_LEVEL_HIGH,
|
||||
.gpio8 = GPIO_LEVEL_HIGH,
|
||||
.gpio9 = GPIO_LEVEL_HIGH,
|
||||
.gpio10 = GPIO_LEVEL_HIGH,
|
||||
.gpio11 = GPIO_LEVEL_HIGH,
|
||||
.gpio12 = GPIO_LEVEL_HIGH,
|
||||
.gpio13 = GPIO_LEVEL_HIGH,
|
||||
.gpio14 = GPIO_LEVEL_HIGH,
|
||||
.gpio15 = GPIO_LEVEL_HIGH,
|
||||
.gpio16 = GPIO_LEVEL_HIGH,
|
||||
.gpio17 = GPIO_LEVEL_HIGH,
|
||||
.gpio18 = GPIO_LEVEL_HIGH,
|
||||
.gpio19 = GPIO_LEVEL_LOW,
|
||||
.gpio20 = GPIO_LEVEL_HIGH,
|
||||
.gpio21 = GPIO_LEVEL_HIGH,
|
||||
.gpio22 = GPIO_LEVEL_LOW,
|
||||
.gpio23 = GPIO_LEVEL_HIGH,
|
||||
.gpio24 = GPIO_LEVEL_LOW,
|
||||
.gpio25 = GPIO_LEVEL_HIGH,
|
||||
.gpio26 = GPIO_LEVEL_HIGH,
|
||||
.gpio27 = GPIO_LEVEL_HIGH,
|
||||
.gpio28 = GPIO_LEVEL_LOW,
|
||||
.gpio29 = GPIO_LEVEL_HIGH,
|
||||
.gpio30 = GPIO_LEVEL_HIGH,
|
||||
.gpio31 = GPIO_LEVEL_LOW,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_invert = {
|
||||
.gpio1 = GPIO_INVERT,
|
||||
.gpio6 = GPIO_INVERT,
|
||||
.gpio13 = GPIO_INVERT,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_reset = {
|
||||
.gpio24 = GPIO_RESET_RSMRST,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set1 pch_gpio_set1_blink = {
|
||||
.gpio18 = GPIO_NO_BLINK,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_mode = {
|
||||
.gpio32 = GPIO_MODE_NATIVE,
|
||||
.gpio33 = GPIO_MODE_GPIO,
|
||||
.gpio34 = GPIO_MODE_GPIO,
|
||||
.gpio35 = GPIO_MODE_GPIO,
|
||||
.gpio36 = GPIO_MODE_GPIO,
|
||||
.gpio37 = GPIO_MODE_GPIO,
|
||||
.gpio38 = GPIO_MODE_GPIO,
|
||||
.gpio39 = GPIO_MODE_GPIO,
|
||||
.gpio40 = GPIO_MODE_NATIVE, // OC1 -USB_PORT1_OC1 - input
|
||||
.gpio41 = GPIO_MODE_NATIVE, // OC2 - pullup
|
||||
.gpio42 = GPIO_MODE_NATIVE, // OC3 -USB_PORT2_OC3 - input
|
||||
.gpio43 = GPIO_MODE_GPIO, // SMB_3B_EN - output
|
||||
.gpio44 = GPIO_MODE_NATIVE,
|
||||
.gpio45 = GPIO_MODE_NATIVE,
|
||||
.gpio46 = GPIO_MODE_NATIVE,
|
||||
.gpio47 = GPIO_MODE_NATIVE,
|
||||
.gpio48 = GPIO_MODE_GPIO,
|
||||
.gpio49 = GPIO_MODE_GPIO,
|
||||
.gpio50 = GPIO_MODE_GPIO,
|
||||
.gpio51 = GPIO_MODE_GPIO,
|
||||
.gpio52 = GPIO_MODE_GPIO,
|
||||
.gpio53 = GPIO_MODE_GPIO,
|
||||
.gpio54 = GPIO_MODE_GPIO,
|
||||
.gpio55 = GPIO_MODE_GPIO,
|
||||
.gpio56 = GPIO_MODE_NATIVE,
|
||||
.gpio57 = GPIO_MODE_GPIO,
|
||||
.gpio58 = GPIO_MODE_NATIVE,
|
||||
.gpio59 = GPIO_MODE_NATIVE, // OC0 -USB_PORT0_OC0 - input
|
||||
.gpio60 = GPIO_MODE_NATIVE,
|
||||
.gpio61 = GPIO_MODE_NATIVE,
|
||||
.gpio62 = GPIO_MODE_NATIVE,
|
||||
.gpio63 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_direction = {
|
||||
.gpio32 = GPIO_DIR_INPUT,
|
||||
.gpio33 = GPIO_DIR_OUTPUT,
|
||||
.gpio34 = GPIO_DIR_INPUT,
|
||||
.gpio35 = GPIO_DIR_INPUT,
|
||||
.gpio36 = GPIO_DIR_INPUT,
|
||||
.gpio37 = GPIO_DIR_INPUT,
|
||||
.gpio38 = GPIO_DIR_INPUT,
|
||||
.gpio39 = GPIO_DIR_INPUT,
|
||||
.gpio40 = GPIO_DIR_INPUT,
|
||||
.gpio41 = GPIO_DIR_INPUT,
|
||||
.gpio42 = GPIO_DIR_INPUT,
|
||||
.gpio43 = GPIO_DIR_OUTPUT,
|
||||
.gpio44 = GPIO_DIR_INPUT,
|
||||
.gpio45 = GPIO_DIR_INPUT,
|
||||
.gpio46 = GPIO_DIR_INPUT,
|
||||
.gpio47 = GPIO_DIR_INPUT,
|
||||
.gpio48 = GPIO_DIR_INPUT,
|
||||
.gpio49 = GPIO_DIR_INPUT,
|
||||
.gpio50 = GPIO_DIR_INPUT,
|
||||
.gpio51 = GPIO_DIR_OUTPUT,
|
||||
.gpio52 = GPIO_DIR_OUTPUT,
|
||||
.gpio53 = GPIO_DIR_OUTPUT,
|
||||
.gpio54 = GPIO_DIR_INPUT,
|
||||
.gpio55 = GPIO_DIR_OUTPUT,
|
||||
.gpio56 = GPIO_DIR_INPUT,
|
||||
.gpio57 = GPIO_DIR_INPUT,
|
||||
.gpio58 = GPIO_DIR_INPUT,
|
||||
.gpio59 = GPIO_DIR_INPUT,
|
||||
.gpio60 = GPIO_DIR_INPUT,
|
||||
.gpio61 = GPIO_DIR_OUTPUT,
|
||||
.gpio62 = GPIO_DIR_OUTPUT,
|
||||
.gpio63 = GPIO_DIR_OUTPUT,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set2 pch_gpio_set2_level = {
|
||||
.gpio32 = GPIO_LEVEL_HIGH,
|
||||
.gpio33 = GPIO_LEVEL_HIGH,
|
||||
.gpio34 = GPIO_LEVEL_LOW,
|
||||
.gpio35 = GPIO_LEVEL_LOW,
|
||||
.gpio36 = GPIO_LEVEL_LOW,
|
||||
.gpio37 = GPIO_LEVEL_LOW,
|
||||
.gpio38 = GPIO_LEVEL_HIGH,
|
||||
.gpio39 = GPIO_LEVEL_LOW,
|
||||
.gpio40 = GPIO_LEVEL_HIGH,
|
||||
.gpio41 = GPIO_LEVEL_HIGH,
|
||||
.gpio42 = GPIO_LEVEL_HIGH,
|
||||
.gpio43 = GPIO_LEVEL_HIGH,
|
||||
.gpio44 = GPIO_LEVEL_HIGH,
|
||||
.gpio45 = GPIO_LEVEL_HIGH,
|
||||
.gpio46 = GPIO_LEVEL_HIGH,
|
||||
.gpio47 = GPIO_LEVEL_HIGH,
|
||||
.gpio48 = GPIO_LEVEL_HIGH,
|
||||
.gpio49 = GPIO_LEVEL_LOW,
|
||||
.gpio50 = GPIO_LEVEL_HIGH,
|
||||
.gpio51 = GPIO_LEVEL_HIGH,
|
||||
.gpio52 = GPIO_LEVEL_HIGH,
|
||||
.gpio53 = GPIO_LEVEL_HIGH,
|
||||
.gpio54 = GPIO_LEVEL_LOW,
|
||||
.gpio55 = GPIO_LEVEL_HIGH,
|
||||
.gpio56 = GPIO_LEVEL_HIGH,
|
||||
.gpio57 = GPIO_LEVEL_HIGH,
|
||||
.gpio58 = GPIO_LEVEL_HIGH,
|
||||
.gpio59 = GPIO_LEVEL_HIGH,
|
||||
.gpio60 = GPIO_LEVEL_HIGH,
|
||||
.gpio61 = GPIO_LEVEL_HIGH,
|
||||
.gpio62 = GPIO_LEVEL_LOW,
|
||||
.gpio63 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_mode = {
|
||||
.gpio64 = GPIO_MODE_GPIO,
|
||||
.gpio65 = GPIO_MODE_GPIO,
|
||||
.gpio66 = GPIO_MODE_GPIO,
|
||||
.gpio67 = GPIO_MODE_GPIO,
|
||||
.gpio68 = GPIO_MODE_GPIO,
|
||||
.gpio69 = GPIO_MODE_GPIO,
|
||||
.gpio70 = GPIO_MODE_GPIO,
|
||||
.gpio71 = GPIO_MODE_GPIO,
|
||||
.gpio72 = GPIO_MODE_NATIVE,
|
||||
.gpio73 = GPIO_MODE_NATIVE,
|
||||
.gpio74 = GPIO_MODE_NATIVE,
|
||||
.gpio75 = GPIO_MODE_NATIVE,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_direction = {
|
||||
.gpio64 = GPIO_DIR_INPUT,
|
||||
.gpio65 = GPIO_DIR_INPUT,
|
||||
.gpio66 = GPIO_DIR_INPUT,
|
||||
.gpio67 = GPIO_DIR_INPUT,
|
||||
.gpio68 = GPIO_DIR_INPUT,
|
||||
.gpio69 = GPIO_DIR_INPUT,
|
||||
.gpio70 = GPIO_DIR_INPUT,
|
||||
.gpio71 = GPIO_DIR_INPUT,
|
||||
.gpio72 = GPIO_DIR_INPUT,
|
||||
.gpio73 = GPIO_DIR_INPUT,
|
||||
.gpio74 = GPIO_DIR_INPUT,
|
||||
.gpio75 = GPIO_DIR_INPUT,
|
||||
};
|
||||
|
||||
const struct pch_gpio_set3 pch_gpio_set3_level = {
|
||||
.gpio64 = GPIO_LEVEL_HIGH,
|
||||
.gpio65 = GPIO_LEVEL_HIGH,
|
||||
.gpio66 = GPIO_LEVEL_HIGH,
|
||||
.gpio67 = GPIO_LEVEL_HIGH,
|
||||
.gpio68 = GPIO_LEVEL_LOW,
|
||||
.gpio69 = GPIO_LEVEL_LOW,
|
||||
.gpio70 = GPIO_LEVEL_LOW,
|
||||
.gpio71 = GPIO_LEVEL_HIGH,
|
||||
.gpio72 = GPIO_LEVEL_HIGH,
|
||||
.gpio73 = GPIO_LEVEL_HIGH,
|
||||
.gpio74 = GPIO_LEVEL_HIGH,
|
||||
.gpio75 = GPIO_LEVEL_HIGH,
|
||||
};
|
||||
|
||||
const struct pch_gpio_map mainboard_gpio_map = {
|
||||
.set1 = {
|
||||
.mode = &pch_gpio_set1_mode,
|
||||
.direction = &pch_gpio_set1_direction,
|
||||
.level = &pch_gpio_set1_level,
|
||||
.invert = &pch_gpio_set1_invert,
|
||||
.reset = &pch_gpio_set1_reset,
|
||||
.blink = &pch_gpio_set1_blink,
|
||||
},
|
||||
.set2 = {
|
||||
.mode = &pch_gpio_set2_mode,
|
||||
.direction = &pch_gpio_set2_direction,
|
||||
.level = &pch_gpio_set2_level,
|
||||
},
|
||||
.set3 = {
|
||||
.mode = &pch_gpio_set3_mode,
|
||||
.direction = &pch_gpio_set3_direction,
|
||||
.level = &pch_gpio_set3_level,
|
||||
},
|
||||
};
|
||||
|
|
@ -0,0 +1,131 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Vendor Name : Realtek
|
||||
* Vendor ID : 0x10ec0269
|
||||
* Subsystem ID : 0x17aa21fb
|
||||
* Revision ID : 0x100203
|
||||
*/
|
||||
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* coreboot specific header */
|
||||
0x10ec0269, // Codec Vendor / Device ID: Realtek ALC269VC
|
||||
0x17aa21fb, // Subsystem ID
|
||||
0x00000013, // Number of 4 dword sets
|
||||
|
||||
/* Bits 31:28 - Codec Address */
|
||||
/* Bits 27:20 - NID */
|
||||
/* Bits 19:8 - Verb ID */
|
||||
/* Bits 7:0 - Payload */
|
||||
|
||||
/* NID 0x01 - NodeInfo */
|
||||
AZALIA_SUBVENDOR(0x0, 0x17AA21FB),
|
||||
|
||||
/* NID 0x0A - External Microphone Connector
|
||||
* Config=0x04A11020 (External,Right; MicIn,3.5mm; Black,JD; DA,Seq)
|
||||
*/
|
||||
AZALIA_PIN_CFG(0x0, 0x0A, 0x04A11020),
|
||||
|
||||
/* NID 0x0B - Headphone Connector
|
||||
* Config=0x0421101F (External,Right; HP,3.5mm; Black,JD; DA,Seq)
|
||||
*/
|
||||
AZALIA_PIN_CFG(0x0, 0x0B, 0x0421101F),
|
||||
|
||||
/* NID 0x0C - Not connected
|
||||
* Config=0x40F000F0 (N/A,N/A; Other,Unknown; Unknown,JD; DA,Seq)
|
||||
*/
|
||||
AZALIA_PIN_CFG(0x0, 0x0C, 0x40F000F0),
|
||||
|
||||
/* NID 0x0D - Internal Speakers
|
||||
* Config=0x90170110 (Fixed,Int; Speaker,Other Analog; Unknown,nJD; DA,Seq)
|
||||
*/
|
||||
AZALIA_PIN_CFG(0x0, 0x0D, 0x90170110),
|
||||
|
||||
/* NID 0x0F - Not connected
|
||||
* Config=0x40F000F0
|
||||
*/
|
||||
AZALIA_PIN_CFG(0x0, 0x0F, 0x40F000F0),
|
||||
|
||||
/* NID 0x11 - Internal Microphone
|
||||
* Config=0xD5A30140 (Fixed internal,Top; Mic In,ATIPI; Unknown,nJD; DA,Seq)
|
||||
*/
|
||||
AZALIA_PIN_CFG(0x0, 0x12, 0x90A60140),
|
||||
AZALIA_PIN_CFG(0x0, 0x14, 0x90170110),
|
||||
AZALIA_PIN_CFG(0x0, 0x15, 0x03211020),
|
||||
AZALIA_PIN_CFG(0x0, 0x17, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0x0, 0x18, 0x03A11830),
|
||||
AZALIA_PIN_CFG(0x0, 0x19, 0x411111F0),
|
||||
|
||||
0x01970804,
|
||||
0x01870803,
|
||||
0x01470740,
|
||||
0x00970600,
|
||||
|
||||
AZALIA_PIN_CFG(0x0, 0x1A, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0x0, 0x1B, 0x411111F0),
|
||||
AZALIA_PIN_CFG(0x0, 0x1D, 0x40138205),
|
||||
AZALIA_PIN_CFG(0x0, 0x1E, 0x411111F0),
|
||||
|
||||
/* Misc entries */
|
||||
0x00370600,
|
||||
0x00270600,
|
||||
0x00B707C0, /* Enable PortB as Output with HP amp */
|
||||
0x00D70740, /* Enable PortD as Output */
|
||||
0x0017A200, /* Disable ClkEn of PortSenseTst */
|
||||
0x0017C621, /* Slave Port - Port A used as microphone input for
|
||||
combo Jack
|
||||
Master Port - Port B used for Jack Presence Detect
|
||||
Enable Combo Jack Detection */
|
||||
0x0017A208, /* Enable ClkEn of PortSenseTst */
|
||||
0x00170500, /* Set power state to D0 */
|
||||
|
||||
/* --- Next Codec --- */
|
||||
|
||||
/* Vendor Name : Intel
|
||||
* Vendor ID : 0x80862806
|
||||
* Subsystem ID : 0x80860101
|
||||
* Revision ID : 0x100000
|
||||
*/
|
||||
/* coreboot specific header */
|
||||
0x80862806, // Codec Vendor / Device ID: Intel PantherPoint HDMI
|
||||
0x80860101, // Subsystem ID
|
||||
0x00000004, // Number of IDs
|
||||
|
||||
/* NID 0x01, HDA Codec Subsystem ID Verb Table: 0x80860101 */
|
||||
AZALIA_SUBVENDOR(0x3, 0x80860101),
|
||||
|
||||
/* Pin Complex (NID 0x05) Digital Out at Int HDMI */
|
||||
AZALIA_PIN_CFG(0x3, 0x05, 0x18560010),
|
||||
|
||||
/* Pin Complex (NID 0x06) Digital Out at Int HDMI */
|
||||
AZALIA_PIN_CFG(0x3, 0x06, 0x18560020),
|
||||
|
||||
/* Pin Complex (NID 0x07) Digital Out at Int HDMI */
|
||||
AZALIA_PIN_CFG(0x3, 0x07, 0x18560030)
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
0x02177a00, /* Digital PCBEEP Gain: 0h=-9db, 1h=-6db ... 4h=+3db, 5h=+6db */
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,82 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2009 coresystems GmbH
|
||||
* Copyright (C) 2011-2012 Google Inc.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <types.h>
|
||||
#include <string.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <console/console.h>
|
||||
#include <drivers/intel/gma/int15.h>
|
||||
#include <arch/acpi.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <smbios.h>
|
||||
#include <device/pci.h>
|
||||
#include <pc80/keyboard.h>
|
||||
#include <ec/lenovo/h8/h8.h>
|
||||
#include <version.h>
|
||||
|
||||
void mainboard_suspend_resume(void)
|
||||
{
|
||||
/* Call SMM finalize() handlers before resume */
|
||||
outb(0xcb, 0xb2);
|
||||
}
|
||||
|
||||
const char *smbios_mainboard_bios_version(void)
|
||||
{
|
||||
static char *s = NULL;
|
||||
|
||||
/* Satisfy thinkpad_acpi. */
|
||||
if (strlen(CONFIG_LOCALVERSION))
|
||||
return "CBET4000 " CONFIG_LOCALVERSION;
|
||||
|
||||
if (s != NULL)
|
||||
return s;
|
||||
s = strconcat("CBET4000 ", coreboot_version);
|
||||
return s;
|
||||
}
|
||||
|
||||
static void mainboard_init(device_t dev)
|
||||
{
|
||||
/* init spi */
|
||||
RCBA32(0x38c8) = 0x00002005;
|
||||
RCBA32(0x38c4) = 0x00802005;
|
||||
RCBA32(0x38c0) = 0x00000007;
|
||||
|
||||
pc_keyboard_init();
|
||||
}
|
||||
|
||||
static void mainboard_enable(device_t dev)
|
||||
{
|
||||
dev->ops->init = mainboard_init;
|
||||
|
||||
install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS,
|
||||
GMA_INT15_PANEL_FIT_DEFAULT,
|
||||
GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
|
||||
}
|
||||
|
||||
void h8_mainboard_init_dock(void)
|
||||
{
|
||||
}
|
||||
|
||||
struct chip_operations mainboard_ops = {
|
||||
.enable_dev = mainboard_enable,
|
||||
};
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007-2010 coresystems GmbH
|
||||
* Copyright (C) 2011 The ChromiumOS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/byteorder.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <console/console.h>
|
||||
#include <northbridge/intel/sandybridge/raminit_native.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
|
||||
void pch_enable_lpc(void)
|
||||
{
|
||||
/* EC Decode Range Port60/64, Port62/66 */
|
||||
/* Enable EC, PS/2 Keyboard/Mouse */
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_EN,
|
||||
CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN |
|
||||
COMA_LPC_EN);
|
||||
|
||||
pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601);
|
||||
pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1);
|
||||
pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1);
|
||||
|
||||
pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10);
|
||||
|
||||
pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000);
|
||||
}
|
||||
|
||||
void rcba_config(void)
|
||||
{
|
||||
/* Disable unused devices (board specific) */
|
||||
RCBA32(FD) = 0x17e81fe3;
|
||||
RCBA32(BUC) = 0;
|
||||
}
|
||||
|
||||
const struct southbridge_usb_port mainboard_usb_ports[] = {
|
||||
{ 1, 0, 0 }, /* P0: , OC 0 */
|
||||
{ 1, 1, 1 }, /* P1: (EHCI debug), OC 1 */
|
||||
{ 1, 1, 3 }, /* P2: OC 3 */
|
||||
{ 1, 0, -1 }, /* P3: no OC */
|
||||
{ 1, 2, -1 }, /* P4: no OC */
|
||||
{ 1, 1, -1 }, /* P5: no OC */
|
||||
{ 1, 1, -1 }, /* P6: no OC */
|
||||
{ 0, 1, -1 }, /* P7: empty, no OC */
|
||||
{ 1, 1, -1 }, /* P8: smart card reader, no OC */
|
||||
{ 1, 0, 5 }, /* P9: (EHCI debug), OC 5 */
|
||||
{ 1, 0, -1 }, /* P10: fingerprint reader, no OC */
|
||||
{ 1, 1, -1 }, /* P11: bluetooth, no OC. */
|
||||
{ 0, 0, -1 }, /* P12: wlan, no OC */
|
||||
{ 1, 1, -1 }, /* P13: camera, no OC */
|
||||
};
|
||||
|
||||
void mainboard_get_spd(spd_raw_data *spd) {
|
||||
read_spd(&spd[0], 0x50);
|
||||
read_spd(&spd[2], 0x51);
|
||||
}
|
||||
|
|
@ -0,0 +1,195 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008-2009 coresystems GmbH
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
|
||||
* MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/io.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/x86/smm.h>
|
||||
#include <ec/acpi/ec.h>
|
||||
#include <ec/lenovo/h8/h8.h>
|
||||
#include <southbridge/intel/bd82x6x/nvs.h>
|
||||
#include <southbridge/intel/bd82x6x/pch.h>
|
||||
#include <southbridge/intel/bd82x6x/me.h>
|
||||
#include <northbridge/intel/sandybridge/sandybridge.h>
|
||||
#include <cpu/intel/model_206ax/model_206ax.h>
|
||||
|
||||
#define GPE_EC_SCI 1
|
||||
#define GPE_EC_WAKE 13
|
||||
|
||||
/* The southbridge SMI handler checks whether gnvs has a
|
||||
* valid pointer before calling the trap handler
|
||||
*/
|
||||
extern global_nvs_t *gnvs;
|
||||
|
||||
static void mainboard_smm_init(void)
|
||||
{
|
||||
printk(BIOS_DEBUG, "initializing SMI\n");
|
||||
/* Enable 0x1600/0x1600 register pair */
|
||||
ec_set_bit(0x00, 0x05);
|
||||
}
|
||||
|
||||
int mainboard_io_trap_handler(int smif)
|
||||
{
|
||||
static int smm_initialized;
|
||||
|
||||
if (!smm_initialized) {
|
||||
mainboard_smm_init();
|
||||
smm_initialized = 1;
|
||||
}
|
||||
|
||||
switch (smif) {
|
||||
default:
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* On success, the IO Trap Handler returns 1
|
||||
* On failure, the IO Trap Handler returns a value != 1 */
|
||||
return 1;
|
||||
}
|
||||
|
||||
static void mainboard_smi_brightness_up(void)
|
||||
{
|
||||
u8 value;
|
||||
|
||||
if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) < 0xf0)
|
||||
pci_write_config8(PCI_DEV(0, 2, 1), 0xf4, (value + 0x10) | 0xf);
|
||||
}
|
||||
|
||||
static void mainboard_smi_brightness_down(void)
|
||||
{
|
||||
u8 value;
|
||||
|
||||
if ((value = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4)) > 0x10)
|
||||
pci_write_config8(PCI_DEV(0, 2, 1), 0xf4,
|
||||
(value - 0x10) & 0xf0);
|
||||
}
|
||||
|
||||
static void mainboard_smi_handle_ec_sci(void)
|
||||
{
|
||||
u8 status = inb(EC_SC);
|
||||
u8 event;
|
||||
|
||||
if (!(status & EC_SCI_EVT))
|
||||
return;
|
||||
|
||||
event = ec_query();
|
||||
printk(BIOS_DEBUG, "EC event %02x\n", event);
|
||||
|
||||
switch (event) {
|
||||
case 0x14:
|
||||
/* brightness up */
|
||||
mainboard_smi_brightness_up();
|
||||
break;
|
||||
case 0x15:
|
||||
/* brightness down */
|
||||
mainboard_smi_brightness_down();
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void mainboard_smi_gpi(u32 gpi_sts)
|
||||
{
|
||||
if (gpi_sts & (1 << GPE_EC_SCI))
|
||||
mainboard_smi_handle_ec_sci();
|
||||
}
|
||||
|
||||
static int mainboard_finalized = 0;
|
||||
|
||||
int mainboard_smi_apmc(u8 data)
|
||||
{
|
||||
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
|
||||
u8 tmp;
|
||||
|
||||
printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase,
|
||||
data);
|
||||
|
||||
if (!pmbase)
|
||||
return 0;
|
||||
|
||||
switch (data) {
|
||||
case APM_CNT_ACPI_ENABLE:
|
||||
/* use 0x1600/0x1604 to prevent races with userspace */
|
||||
ec_set_ports(0x1604, 0x1600);
|
||||
/* route EC_SCI to SCI */
|
||||
outw(inw(pmbase + ALT_GP_SMI_EN) & ~(1 << GPE_EC_SCI), pmbase + ALT_GP_SMI_EN);
|
||||
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
|
||||
tmp &= ~0x03;
|
||||
tmp |= 0x02;
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
case APM_CNT_ACPI_DISABLE:
|
||||
/* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't
|
||||
provide a EC query function */
|
||||
ec_set_ports(0x66, 0x62);
|
||||
/* route EC_SCI# to SMI */
|
||||
outw(inw(pmbase + ALT_GP_SMI_EN) | (1 << GPE_EC_SCI),
|
||||
pmbase + ALT_GP_SMI_EN);
|
||||
tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb);
|
||||
tmp &= ~0x03;
|
||||
tmp |= 0x01;
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp);
|
||||
/* discard all events, and enable attention */
|
||||
ec_write(0x80, 0x01);
|
||||
break;
|
||||
case APM_CNT_FINALIZE:
|
||||
printk(BIOS_DEBUG, "APMC: FINALIZE\n");
|
||||
if (mainboard_finalized) {
|
||||
printk(BIOS_DEBUG, "APMC#: Already finalized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
intel_me_finalize_smm();
|
||||
intel_pch_finalize_smm();
|
||||
intel_sandybridge_finalize_smm();
|
||||
intel_model_206ax_finalize_smm();
|
||||
|
||||
mainboard_finalized = 1;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
void mainboard_smi_sleep(u8 slp_typ)
|
||||
{
|
||||
if (slp_typ == 3) {
|
||||
u8 ec_wake = ec_read(0x32);
|
||||
/* If EC wake events are enabled, enable wake on EC WAKE GPE. */
|
||||
if (ec_wake & 0x14) {
|
||||
u32 gpe_rout;
|
||||
u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc;
|
||||
|
||||
/* Enable EC WAKE GPE. */
|
||||
outl(inl(pmbase + GPE0_EN) | (1 << (GPE_EC_WAKE + 16)), pmbase + GPE0_EN);
|
||||
gpe_rout = pci_read_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT);
|
||||
/* Redirect EC WAKE GPE to SCI. */
|
||||
gpe_rout &= ~(3 << (GPE_EC_WAKE * 2));
|
||||
gpe_rout |= (2 << (GPE_EC_WAKE * 2));
|
||||
pci_write_config32(PCI_DEV(0, 0x1f, 0), GPIO_ROUT, gpe_rout);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
|
||||
* Copyright (C) 2014 Vladimir Serbinenko
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef T430S_THERMAL_H
|
||||
#define T430S_THERMAL_H
|
||||
|
||||
/* Temperature which OS will shutdown at */
|
||||
#define CRITICAL_TEMPERATURE 100
|
||||
|
||||
/* Temperature which OS will throttle CPU */
|
||||
#define PASSIVE_TEMPERATURE 90
|
||||
|
||||
#endif /* T430S_THERMAL_H */
|
||||
Loading…
Reference in New Issue