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nb/intel/sandybridge: Add print for PLL_REF100_CFG 

This field can take eight different values, depending on the maximum
supported speed for the memory when using the 100 MHz reference clock.

Change-Id: I8f2f04f9444831319d4f7bf0d246d01030b6f864
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Angel Pons 2020-03-23 22:51:05 +01:00 committed by Patrick Georgi
parent a6c8b4becb
commit 29f391ec8f
1 changed files with 3 additions and 1 deletions
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4
src/northbridge/intel/sandybridge/raminit_ivy.c
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@ -176,10 +176,12 @@ static void find_cas_tck(ramctr_timing *ctrl)
/* 100 MHz reference clock supported */
reg32 = pci_read_config32(HOST_BRIDGE, CAPID0_B);
ref_100mhz_support = !!((reg32 >> 21) & 0x7);
ref_100mhz_support = (reg32 >> 21) & 0x7;
printk(BIOS_DEBUG, "100MHz reference clock support: %s\n", ref_100mhz_support ? "yes"
: "no");
printk(BIOS_DEBUG, "PLL_REF100_CFG value: 0x%x\n", ref_100mhz_support);
/* Find CAS latency */
while (1) {
/*