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soc/intel/skylake: Enable HECI BAR for ME communication

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This patch programs and enables BAR for ME (bus:0/
device:0x16/function:0) device to have early ME communication.

BUG=none
BRANCH=none
TEST=Verified Global Reset MEI message can able to perform platform
global reset during romstage.

Change-Id: I99ce0ccd42610112a361a48ba31168c9feaa0332
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/17016
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Subrata Banik 2016-10-13 18:05:04 +05:30 committed by Aaron Durbin
parent c68ab5e8e5
commit 29f8708fca
2 changed files with 25 additions and 0 deletions
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23
src/soc/intel/skylake/bootblock/pch.c
View file

@ -251,6 +251,27 @@ static void soc_config_rtc(void)
B_PCH_PCR_RTC_CONF_UCMOS_EN); B_PCH_PCR_RTC_CONF_UCMOS_EN);
} }
static void enable_heci(void)
{
device_t dev = PCH_DEV_ME;
u8 pcireg;
/* Assign Resources to HECI1 */
/* Clear BIT 1-2 of Command Register */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
pci_write_config8(dev, PCI_COMMAND, pcireg);
/* Program Temporary BAR for HECI1 */
pci_write_config32(dev, PCI_BASE_ADDRESS_0, HECI1_BASE_ADDRESS);
pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0);
/* Enable Bus Master and MMIO Space */
pcireg = pci_read_config8(dev, PCI_COMMAND);
pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config8(dev, PCI_COMMAND, pcireg);
}
void pch_early_init(void) void pch_early_init(void)
{ {
/* /*
@ -281,4 +302,6 @@ void pch_early_init(void)
enable_smbus(); enable_smbus();
soc_config_rtc(); soc_config_rtc();
enable_heci();
} }

2
src/soc/intel/skylake/include/soc/iomap.h
View file

@ -56,6 +56,8 @@
#define GPIO_BASE_SIZE 0x10000 #define GPIO_BASE_SIZE 0x10000
#define HECI1_BASE_ADDRESS 0xfed1a000
/* /*
* I/O port address space * I/O port address space
*/ */