Fix the indent and whitespace to match LinuxBIOS standards
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2651 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Jordan Crouse
Stefan Reinauer
parent
9934b813da
commit
2a133f7851
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@ -21,26 +21,26 @@
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#ifndef _SOUTHBRIDGE_AMD_CS5536
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#define _SOUTHBRIDGE_AMD_CS5536
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#define MAX_UNWANTED_VPCI 8 /* increase if needed */
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#define MAX_UNWANTED_VPCI 8 /* increase if needed */
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extern struct chip_operations southbridge_amd_cs5536_ops;
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struct southbridge_amd_cs5536_config {
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unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */
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unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */
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unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */
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unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
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unsigned int lpc_serirq_enable; /* interrupt enables for LPC bus; each bit is an irq 0-15 */
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unsigned int lpc_serirq_polarity; /* LPC IRQ polarity; each bit is an irq 0-15 */
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unsigned char lpc_serirq_mode; /* 0:Continuous 1:Quiet */
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unsigned int enable_gpio_int_route; /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
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unsigned char enable_ide_nand_flash; /* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */
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unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */
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unsigned char enable_USBP4_device; /* Enable USB Port 4 0:host 1:device */
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unsigned int enable_USBP4_overcurrent; /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */
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unsigned char com1_enable; /* enable COM1 */
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unsigned int com1_address; /* e.g. 0x3F8 */
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unsigned int com1_irq; /* e.g. 4 */
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unsigned char com2_enable; /* enable COM2 */
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unsigned int com2_address; /* e.g. 0x2F8 */
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unsigned int com2_irq; /* e.g. 3 */
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unsigned char com1_enable; /* enable COM1 */
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unsigned int com1_address; /* e.g. 0x3F8 */
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unsigned int com1_irq; /* e.g. 4 */
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unsigned char com2_enable; /* enable COM2 */
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unsigned int com2_address; /* e.g. 0x2F8 */
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unsigned int com2_irq; /* e.g. 3 */
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unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */
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};
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#endif /* _SOUTHBRIDGE_AMD_CS5536 */
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#endif /* _SOUTHBRIDGE_AMD_CS5536 */
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@ -41,23 +41,23 @@ struct msrinit {
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/* Master Configuration Register for Bus Masters.*/
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struct msrinit SB_MASTER_CONF_TABLE[] = {
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{USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}},
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{ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000}},
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{AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}},
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{MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000}},
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{0,{0,0}}
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{USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
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{ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}},
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{AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}},
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{MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000}},
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{0, {0, 0}}
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};
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/* 5536 Clock Gating*/
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struct msrinit CS5536_CLOCK_GATING_TABLE[] = {
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/* MSR Setting*/
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{GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}},
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{GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
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{GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}},
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{MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/
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{ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
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{AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}},
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{0,{0,0}}
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/* MSR Setting*/
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{GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
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{GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
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{GLCP_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}},
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{MDD_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */
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{ATA_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
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{AC97_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}},
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{0, {0, 0}}
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};
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struct acpiinit {
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@ -73,24 +73,24 @@ struct acpiinit acpi_init_table[] = {
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{ACPI_IO_BASE + 0x18, 0x0FFFFFFFF},
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{ACPI_IO_BASE + 0x00, 0x0000FFFF},
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{PMS_IO_BASE + PM_SCLK, 0x000000E00},
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{PMS_IO_BASE + PM_SED, 0x000004601},
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{PMS_IO_BASE + PM_SED, 0x000004601},
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{PMS_IO_BASE + PM_SIDD, 0x000008C02},
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{PMS_IO_BASE + PM_WKD, 0x0000000A0},
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{PMS_IO_BASE + PM_WKD, 0x0000000A0},
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{PMS_IO_BASE + PM_WKXD, 0x0000000A0},
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{0,0,0}
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{0, 0, 0}
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};
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struct FLASH_DEVICE {
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unsigned char fType; /* Flash type: NOR or NAND */
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unsigned char fType; /* Flash type: NOR or NAND */
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unsigned char fInterface; /* Flash interface: I/O or Memory */
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unsigned long fMask; /* Flash size/mask */
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unsigned long fMask; /* Flash size/mask */
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};
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struct FLASH_DEVICE FlashInitTable[] = {
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{ FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */
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{ FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */
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{ FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */
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{ FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */
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{FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */
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{FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */
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{FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */
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{FLASH_TYPE_NONE, 0, 0}, /* CS3, or Flash Device 3 */
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};
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#define FlashInitTableLen (sizeof(FlashInitTable)/sizeof(FlashInitTable[0]))
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@ -100,8 +100,7 @@ uint32_t FlashPort[] = {
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MDD_LBAR_FLSH1,
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MDD_LBAR_FLSH2,
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MDD_LBAR_FLSH3
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};
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};
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/* ***************************************************************************/
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/* **/
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@ -110,39 +109,39 @@ uint32_t FlashPort[] = {
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/* * Program ACPI LBAR and initialize ACPI registers.*/
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/* **/
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/* ***************************************************************************/
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static void pmChipsetInit(void) {
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static void pmChipsetInit(void)
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{
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uint32_t val = 0;
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uint16_t port;
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port = (PMS_IO_BASE + 0x010);
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val = 0x0E00 ; /* 1ms*/
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port = (PMS_IO_BASE + 0x010);
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val = 0x0E00; /* 1ms */
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outl(val, port);
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/* PM_WKXD*/
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/* Make sure bits[3:0]=0000b to clear the*/
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/* saved Sx state*/
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port = (PMS_IO_BASE + 0x034);
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val = 0x0A0 ; /* 5ms*/
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/* PM_WKXD */
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/* Make sure bits[3:0]=0000b to clear the */
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/* saved Sx state */
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port = (PMS_IO_BASE + 0x034);
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val = 0x0A0; /* 5ms */
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outl(val, port);
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/* PM_WKD*/
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port = (PMS_IO_BASE + 0x030);
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/* PM_WKD */
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port = (PMS_IO_BASE + 0x030);
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outl(val, port);
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/* PM_SED*/
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port = (PMS_IO_BASE + 0x014);
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/* PM_SED */
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port = (PMS_IO_BASE + 0x014);
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/* mov eax, 0x057642 ; 100ms, works*/
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val = 0x04601 ; /* 5ms*/
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val = 0x04601; /* 5ms */
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outl(val, port);
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/* PM_SIDD*/
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port = (PMS_IO_BASE + 0x020);
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/* PM_SIDD */
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port = (PMS_IO_BASE + 0x020);
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/* mov eax, 0x0AEC84 ; 200ms, works*/
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val = 0x08C02 ; /* 10ms*/
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val = 0x08C02; /* 10ms */
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outl(val, port);
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}
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/***************************************************************************
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*
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* ChipsetFlashSetup
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@ -152,7 +151,8 @@ static void pmChipsetInit(void) {
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* configured (don't call it if you want IDE).
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*
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**************************************************************************/
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static void ChipsetFlashSetup(void){
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static void ChipsetFlashSetup(void)
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{
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msr_t msr;
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int i;
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int numEnabled = 0;
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@ -173,13 +173,15 @@ static void ChipsetFlashSetup(void){
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else
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msr.hi &= ~0x00000004;
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msr.hi |= FlashInitTable[i].fMask;
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printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
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printk_debug("MSR(0x%08X, %08X_%08X)\n", FlashPort[i],
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msr.hi, msr.lo);
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wrmsr(FlashPort[i], msr);
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/* now write-enable the device */
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msr = rdmsr(MDD_NORF_CNTRL);
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msr.lo |= (1 << i);
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printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
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printk_debug("MSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL,
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msr.hi, msr.lo);
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wrmsr(MDD_NORF_CNTRL, msr);
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/* update the number enabled */
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@ -190,24 +192,26 @@ static void ChipsetFlashSetup(void){
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printk_debug("ChipsetFlashSetup: Finish\n");
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}
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/* ***************************************************************************/
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/* **/
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/* * enable_ide_nand_flash_header */
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/* Run after VSA init to enable the flash PCI device header */
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/* **/
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/* ***************************************************************************/
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static void enable_ide_nand_flash_header(){
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/* Tell VSA to use FLASH PCI header. Not IDE header.*/
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static void enable_ide_nand_flash_header()
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{
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/* Tell VSA to use FLASH PCI header. Not IDE header. */
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outl(0x80007A40, 0xCF8);
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outl(0xDEADBEEF, 0xCFC);
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}
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#define RTC_CENTURY 0x32
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#define RTC_DOMA 0x3D
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#define RTC_MONA 0x3E
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static void lpc_init(struct southbridge_amd_cs5536_config *sb){
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static void lpc_init(struct southbridge_amd_cs5536_config *sb)
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{
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msr_t msr;
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if (sb->lpc_serirq_enable) {
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@ -216,7 +220,7 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb){
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wrmsr(MDD_IRQM_LPC, msr);
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if (sb->lpc_serirq_polarity) {
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msr.lo = sb->lpc_serirq_polarity << 16;
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msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */
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msr.lo |= (sb->lpc_serirq_mode << 6) | (1 << 7); /* enable */
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msr.hi = 0;
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wrmsr(MDD_LPC_SIRQ, msr);
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}
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@ -246,43 +250,44 @@ static void lpc_init(struct southbridge_amd_cs5536_config *sb){
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isa_dma_init();
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}
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static void uarts_init(struct southbridge_amd_cs5536_config *sb){
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static void uarts_init(struct southbridge_amd_cs5536_config *sb)
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{
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msr_t msr;
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uint16_t addr;
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uint32_t gpio_addr;
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device_t dev;
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dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
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dev = dev_find_device(PCI_VENDOR_ID_AMD,
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PCI_DEVICE_ID_AMD_CS5536_ISA, 0);
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gpio_addr = pci_read_config32(dev, PCI_BASE_ADDRESS_1);
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gpio_addr &= ~1; /* clear IO bit */
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gpio_addr &= ~1; /* clear IO bit */
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printk_debug("GPIO_ADDR: %08X\n", gpio_addr);
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/* This could be extended to support IR modes */
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/* COM1 */
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if (sb->com1_enable){
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if (sb->com1_enable) {
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/* Set the address */
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switch (sb->com1_address){
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case 0x3F8:
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switch (sb->com1_address) {
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case 0x3F8:
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addr = 7;
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break;
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case 0x3E8:
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case 0x3E8:
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addr = 6;
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break;
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case 0x2F8:
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case 0x2F8:
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addr = 5;
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break;
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case 0x2E8:
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case 0x2E8:
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addr = 4;
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break;
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}
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msr = rdmsr(MDD_LEG_IO);
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msr.lo |= addr << 16;
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wrmsr(MDD_LEG_IO,msr);
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wrmsr(MDD_LEG_IO, msr);
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/* Set the IRQ */
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msr = rdmsr(MDD_IRQM_YHIGH);
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@ -301,8 +306,9 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
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/* Set: INAUX1 Select (0x34) */
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outl(GPIOL_9_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
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/* Set: GPIO 8 + 9 Pull Up (0x18) */
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outl(GPIOL_8_SET | GPIOL_9_SET, gpio_addr + GPIOL_PULLUP_ENABLE);
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/* Set: GPIO 8 + 9 Pull Up (0x18) */
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outl(GPIOL_8_SET | GPIOL_9_SET,
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gpio_addr + GPIOL_PULLUP_ENABLE);
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/* enable COM1 */
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/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
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@ -310,47 +316,45 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
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msr.hi = 0;
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wrmsr(MDD_UART1_CONF, msr);
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}
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else{
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} else {
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/* Reset and disable COM1 */
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printk_err("Not disabling COM1 due to a bug ...\n");
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/* for now, don't do this! */
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return;
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msr = rdmsr(MDD_UART1_CONF);
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msr.lo = 1; // reset
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msr.lo = 1; // reset
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wrmsr(MDD_UART1_CONF, msr);
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msr.lo = 0; // disabled
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msr.lo = 0; // disabled
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wrmsr(MDD_UART1_CONF, msr);
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/* Disable the IRQ */
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msr = rdmsr(MDD_LEG_IO);
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msr.lo |= ~(0xF << 16);
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wrmsr(MDD_LEG_IO,msr);
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wrmsr(MDD_LEG_IO, msr);
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}
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/* COM2 */
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if (sb->com2_enable){
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switch (sb->com2_address){
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case 0x3F8:
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if (sb->com2_enable) {
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switch (sb->com2_address) {
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case 0x3F8:
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addr = 7;
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break;
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case 0x3E8:
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case 0x3E8:
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addr = 6;
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break;
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case 0x2F8:
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case 0x2F8:
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addr = 5;
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break;
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case 0x2E8:
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case 0x2E8:
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addr = 4;
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break;
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}
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msr = rdmsr(MDD_LEG_IO);
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msr.lo |= addr << 20;
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wrmsr(MDD_LEG_IO,msr);
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wrmsr(MDD_LEG_IO, msr);
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/* Set the IRQ */
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msr = rdmsr(MDD_IRQM_YHIGH);
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@ -361,7 +365,7 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
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/* Set: Output Enable (0x4) */
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outl(GPIOL_3_SET, gpio_addr + GPIOL_OUTPUT_ENABLE);
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/* Set: OUTAUX1 Select (0x10) */
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outl(GPIOL_3_SET,gpio_addr + GPIOL_OUT_AUX1_SELECT);
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outl(GPIOL_3_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT);
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/* GPIO4 - UART2_TX */
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/* Set: Input Enable (0x20) */
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@ -369,8 +373,9 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
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/* Set: INAUX1 Select (0x34) */
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outl(GPIOL_4_SET, gpio_addr + GPIOL_IN_AUX1_SELECT);
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/* Set: GPIO 3 + 3 Pull Up (0x18) */
|
||||
outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE);
|
||||
/* Set: GPIO 3 + 3 Pull Up (0x18) */
|
||||
outl(GPIOL_3_SET | GPIOL_4_SET,
|
||||
gpio_addr + GPIOL_PULLUP_ENABLE);
|
||||
|
||||
/* enable COM2 */
|
||||
/* Bit 1 = device enable Bit 4 = allow access to the upper banks */
|
||||
|
|
@ -378,48 +383,44 @@ static void uarts_init(struct southbridge_amd_cs5536_config *sb){
|
|||
msr.hi = 0;
|
||||
wrmsr(MDD_UART2_CONF, msr);
|
||||
|
||||
}
|
||||
else{
|
||||
} else {
|
||||
/* Reset and disable COM2 */
|
||||
msr = rdmsr(MDD_UART2_CONF);
|
||||
msr.lo = 1; // reset
|
||||
msr.lo = 1; // reset
|
||||
wrmsr(MDD_UART2_CONF, msr);
|
||||
msr.lo = 0; // disabled
|
||||
msr.lo = 0; // disabled
|
||||
wrmsr(MDD_UART2_CONF, msr);
|
||||
|
||||
/* Disable the IRQ */
|
||||
msr = rdmsr(MDD_LEG_IO);
|
||||
msr.lo |= ~(0xF << 20);
|
||||
wrmsr(MDD_LEG_IO,msr);
|
||||
wrmsr(MDD_LEG_IO, msr);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
#define HCCPARAMS 0x08
|
||||
#define IPREG04 0xA0
|
||||
#define USB_HCCPW_SET (1 << 1)
|
||||
#define UOCCAP 0x00
|
||||
#define APU_SET (1 << 15)
|
||||
#define UOCMUX 0x04
|
||||
#define PMUX_HOST 0x02
|
||||
#define PMUX_DEVICE 0x03
|
||||
#define PMUX_HOST 0x02
|
||||
#define PMUX_DEVICE 0x03
|
||||
#define PUEN_SET (1 << 2)
|
||||
#define UDCDEVCTL 0x404
|
||||
#define UDC_SD_SET (1 << 10)
|
||||
#define UOCCTL 0x0C
|
||||
#define PADEN_SET (1 << 7)
|
||||
|
||||
|
||||
static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
|
||||
{
|
||||
uint32_t * bar;
|
||||
uint32_t *bar;
|
||||
msr_t msr;
|
||||
device_t dev;
|
||||
|
||||
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
|
||||
if(dev){
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_EHCI, 0);
|
||||
if (dev) {
|
||||
|
||||
/* Serial Short Detect Enable */
|
||||
msr = rdmsr(USB2_SB_GLD_MSR_CONF);
|
||||
|
|
@ -427,7 +428,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
|
|||
wrmsr(USB2_SB_GLD_MSR_CONF, msr);
|
||||
|
||||
/* write to clear diag register */
|
||||
wrmsr(USB2_SB_GLD_MSR_DIAG,rdmsr(USB2_SB_GLD_MSR_DIAG));
|
||||
wrmsr(USB2_SB_GLD_MSR_DIAG, rdmsr(USB2_SB_GLD_MSR_DIAG));
|
||||
|
||||
bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
|
||||
|
|
@ -438,9 +439,9 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
|
|||
*(bar + HCCPARAMS) = 0x00005012;
|
||||
}
|
||||
|
||||
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
|
||||
if(dev){
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
|
||||
if (dev) {
|
||||
bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
|
||||
*(bar + UOCMUX) &= PUEN_SET;
|
||||
|
|
@ -448,8 +449,7 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
|
|||
/* Host or Device? */
|
||||
if (sb->enable_USBP4_device) {
|
||||
*(bar + UOCMUX) |= PMUX_DEVICE;
|
||||
}
|
||||
else{
|
||||
} else {
|
||||
*(bar + UOCMUX) |= PMUX_HOST;
|
||||
}
|
||||
|
||||
|
|
@ -460,35 +460,41 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
|
|||
}
|
||||
|
||||
/* PBz#6466: If the UOC(OTG) device, port 4, is configured as a device,
|
||||
* then perform the following sequence:
|
||||
* then perform the following sequence:
|
||||
*
|
||||
* - set SD bit in DEVCTRL udc register
|
||||
* - set PADEN (former OTGPADEN) bit in uoc register
|
||||
* - set APU bit in uoc register */
|
||||
if (sb->enable_USBP4_device) {
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
|
||||
if(dev){
|
||||
bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
|
||||
if (dev) {
|
||||
bar = (uint32_t *) pci_read_config32(dev,
|
||||
PCI_BASE_ADDRESS_0);
|
||||
*(bar + UDCDEVCTL) |= UDC_SD_SET;
|
||||
|
||||
}
|
||||
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
|
||||
if(dev){
|
||||
bar = (uint32_t *) pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
|
||||
if (dev) {
|
||||
bar = (uint32_t *) pci_read_config32(dev,
|
||||
PCI_BASE_ADDRESS_0);
|
||||
*(bar + UOCCTL) |= PADEN_SET;
|
||||
*(bar + UOCCAP) |= APU_SET;
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable virtual PCI UDC and OTG headers */
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
|
||||
if(dev){
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_UDC, 0);
|
||||
if (dev) {
|
||||
pci_write_config8(dev, 0x7C, 0xDEADBEEF);
|
||||
}
|
||||
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
|
||||
if(dev){
|
||||
dev = dev_find_device(PCI_VENDOR_ID_AMD,
|
||||
PCI_DEVICE_ID_AMD_CS5536_OTG, 0);
|
||||
if (dev) {
|
||||
pci_write_config8(dev, 0x7C, 0xDEADBEEF);
|
||||
}
|
||||
}
|
||||
|
|
@ -499,20 +505,22 @@ static void enable_USB_port4(struct southbridge_amd_cs5536_config *sb)
|
|||
/* Called from northbridge init (Pre-VSA). */
|
||||
/* **/
|
||||
/* ***************************************************************************/
|
||||
void chipsetinit (void){
|
||||
void chipsetinit(void)
|
||||
{
|
||||
device_t dev;
|
||||
msr_t msr;
|
||||
uint32_t msrnum;
|
||||
struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
|
||||
struct southbridge_amd_cs5536_config *sb =
|
||||
(struct southbridge_amd_cs5536_config *)dev->chip_info;
|
||||
struct msrinit *csi;
|
||||
|
||||
outb( P80_CHIPSET_INIT, 0x80);
|
||||
outb(P80_CHIPSET_INIT, 0x80);
|
||||
|
||||
/* we hope NEVER to be in linuxbios when S3 resumes
|
||||
if (! IsS3Resume()) */
|
||||
if (! IsS3Resume()) */
|
||||
{
|
||||
struct acpiinit *aci = acpi_init_table;
|
||||
for(; aci->ioreg; aci++) {
|
||||
for (; aci->ioreg; aci++) {
|
||||
outl(aci->regdata, aci->ioreg);
|
||||
inl(aci->ioreg);
|
||||
}
|
||||
|
|
@ -520,43 +528,42 @@ void chipsetinit (void){
|
|||
pmChipsetInit();
|
||||
}
|
||||
|
||||
|
||||
/* set hd IRQ */
|
||||
outl( GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
|
||||
outl( GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
|
||||
outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
|
||||
outl(GPIOL_2_SET, GPIO_IO_BASE + GPIOL_IN_AUX1_SELECT);
|
||||
|
||||
/* Allow IO read and writes during a ATA DMA operation.*/
|
||||
/* This could be done in the HD rom but do it here for easier debugging.*/
|
||||
/* Allow IO read and writes during a ATA DMA operation. */
|
||||
/* This could be done in the HD rom but do it here for easier debugging. */
|
||||
msrnum = ATA_SB_GLD_MSR_ERR;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo &= ~0x100;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
/* Enable Post Primary IDE.*/
|
||||
/* Enable Post Primary IDE. */
|
||||
msrnum = GLPCI_SB_CTRL;
|
||||
msr = rdmsr(msrnum);
|
||||
msr.lo |= GLPCI_CRTL_PPIDE_SET;
|
||||
msr.lo |= GLPCI_CRTL_PPIDE_SET;
|
||||
wrmsr(msrnum, msr);
|
||||
|
||||
|
||||
csi = SB_MASTER_CONF_TABLE;
|
||||
for(; csi->msrnum; csi++){
|
||||
for (; csi->msrnum; csi++) {
|
||||
msr.lo = csi->msr.lo;
|
||||
msr.hi = csi->msr.hi;
|
||||
wrmsr(csi->msrnum, msr); // MSR - see table above
|
||||
wrmsr(csi->msrnum, msr); // MSR - see table above
|
||||
}
|
||||
|
||||
/* Flash BAR size Setup*/
|
||||
printk_err("%sDoing ChipsetFlashSetup()\n", sb->enable_ide_nand_flash == 1 ? "" : "Not ");
|
||||
/* Flash BAR size Setup */
|
||||
printk_err("%sDoing ChipsetFlashSetup()\n",
|
||||
sb->enable_ide_nand_flash == 1 ? "" : "Not ");
|
||||
if (sb->enable_ide_nand_flash == 1)
|
||||
ChipsetFlashSetup();
|
||||
|
||||
/* */
|
||||
/* Set up Hardware Clock Gating*/
|
||||
/* Set up Hardware Clock Gating */
|
||||
/* */
|
||||
{
|
||||
csi = CS5536_CLOCK_GATING_TABLE;
|
||||
for(; csi->msrnum; csi++){
|
||||
for (; csi->msrnum; csi++) {
|
||||
msr.lo = csi->msr.lo;
|
||||
msr.hi = csi->msr.hi;
|
||||
wrmsr(csi->msrnum, msr); // MSR - see table above
|
||||
|
|
@ -566,7 +573,8 @@ void chipsetinit (void){
|
|||
|
||||
static void southbridge_init(struct device *dev)
|
||||
{
|
||||
struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
|
||||
struct southbridge_amd_cs5536_config *sb =
|
||||
(struct southbridge_amd_cs5536_config *)dev->chip_info;
|
||||
int i;
|
||||
/*
|
||||
* struct device *gpiodev;
|
||||
|
|
@ -578,12 +586,15 @@ static void southbridge_init(struct device *dev)
|
|||
lpc_init(sb);
|
||||
uarts_init(sb);
|
||||
|
||||
if (sb->enable_gpio_int_route){
|
||||
vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB, (sb->enable_gpio_int_route & 0xFFFF));
|
||||
vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD, (sb->enable_gpio_int_route >> 16));
|
||||
if (sb->enable_gpio_int_route) {
|
||||
vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_AB,
|
||||
(sb->enable_gpio_int_route & 0xFFFF));
|
||||
vrWrite((VRC_MISCELLANEOUS << 8) + PCI_INT_CD,
|
||||
(sb->enable_gpio_int_route >> 16));
|
||||
}
|
||||
|
||||
printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__, sb->enable_ide_nand_flash);
|
||||
printk_err("cs5536: %s: enable_ide_nand_flash is %d\n", __FUNCTION__,
|
||||
sb->enable_ide_nand_flash);
|
||||
if (sb->enable_ide_nand_flash == 1) {
|
||||
enable_ide_nand_flash_header();
|
||||
}
|
||||
|
|
@ -592,13 +603,13 @@ static void southbridge_init(struct device *dev)
|
|||
|
||||
/* disable unwanted virtual PCI devices */
|
||||
for (i = 0; (i < MAX_UNWANTED_VPCI) && (0 != sb->unwanted_vpci[i]); i++) {
|
||||
printk_debug("Disabling VPCI device: 0x%08X\n", sb->unwanted_vpci[i]);
|
||||
printk_debug("Disabling VPCI device: 0x%08X\n",
|
||||
sb->unwanted_vpci[i]);
|
||||
outl(sb->unwanted_vpci[i] + 0x7C, 0xCF8);
|
||||
outl(0xDEADBEEF, 0xCFC);
|
||||
outl(0xDEADBEEF, 0xCFC);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
static void southbridge_enable(struct device *dev)
|
||||
{
|
||||
printk_err("cs5536: %s: dev is %p\n", __FUNCTION__, dev);
|
||||
|
|
@ -613,24 +624,24 @@ static void cs5536_pci_dev_enable_resources(device_t dev)
|
|||
}
|
||||
|
||||
static struct device_operations southbridge_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = cs5536_pci_dev_enable_resources,
|
||||
.init = southbridge_init,
|
||||
// .enable = southbridge_enable,
|
||||
.scan_bus = scan_static_bus,
|
||||
.init = southbridge_init,
|
||||
// .enable = southbridge_enable,
|
||||
.scan_bus = scan_static_bus,
|
||||
};
|
||||
|
||||
static struct pci_driver cs5536_pci_driver __pci_driver = {
|
||||
.ops = &southbridge_ops,
|
||||
.ops = &southbridge_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_AMD_CS5536_ISA
|
||||
};
|
||||
|
||||
struct chip_operations southbridge_amd_cs5536_ops = {
|
||||
CHIP_NAME("AMD Geode CS5536 Southbridge")
|
||||
/* This is only called when this device is listed in the
|
||||
* static device tree.
|
||||
*/
|
||||
.enable_dev = southbridge_enable,
|
||||
/* This is only called when this device is listed in the
|
||||
* static device tree.
|
||||
*/
|
||||
.enable_dev = southbridge_enable,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -23,21 +23,21 @@
|
|||
#define Cx5536_ID ( 0x208F1022)
|
||||
|
||||
/* SouthBridge Equates */
|
||||
#define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
|
||||
#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
|
||||
#define CS5536_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
|
||||
#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
|
||||
#define MSR_SB ((CS5536_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */
|
||||
#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
|
||||
#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
|
||||
|
||||
#define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */
|
||||
#define CS5536_DEV_NUM 0x0F /* default PCI device number for CS5536 */
|
||||
#define SMBUS_IO_BASE 0x6000
|
||||
#define GPIO_IO_BASE 0x6100
|
||||
#define MFGPT_IO_BASE 0x6200
|
||||
#define ACPI_IO_BASE 0x9C00
|
||||
#define PMS_IO_BASE 0x9D00
|
||||
|
||||
#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15
|
||||
#define CS5535_IDSEL 0x02000000 // IDSEL = AD25, device #15
|
||||
#define CHIPSET_DEV_NUM 15
|
||||
#define IDSEL_BASE 11 // bit 11 = device 1
|
||||
#define IDSEL_BASE 11 // bit 11 = device 1
|
||||
|
||||
/* Cs5536 as follows. */
|
||||
/* SB_GLIU */
|
||||
|
|
@ -50,8 +50,8 @@
|
|||
/* port6 - USB Controller #1 */
|
||||
/* port7 - GLCP */
|
||||
|
||||
#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
|
||||
#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
|
||||
#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
|
||||
#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
|
||||
#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
|
||||
#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
|
||||
#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
|
||||
|
|
@ -78,13 +78,13 @@
|
|||
/* */
|
||||
#define USB2_SB_GLD_MSR_CAP (MSR_SB_USB2 + 0x00)
|
||||
#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)
|
||||
#define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */
|
||||
#define USB2_UPPER_SSDEN_SET (1 << 3 ) /* Bit 35 */
|
||||
#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
|
||||
#define USB2_SB_GLD_MSR_DIAG (MSR_SB_USB2 + 0x05)
|
||||
#define USB2_SB_GLD_MSR_OHCI_BASE (MSR_SB_USB2 + 0x08)
|
||||
#define USB2_SB_GLD_MSR_EHCI_BASE (MSR_SB_USB2 + 0x09)
|
||||
#define USB2_SB_GLD_MSR_DEVCTL_BASE (MSR_SB_USB2 + 0x0A)
|
||||
#define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */
|
||||
#define USB2_SB_GLD_MSR_UOC_BASE (MSR_SB_USB2 + 0x0B) /* Option controller base */
|
||||
|
||||
/* */
|
||||
/* ATA*/
|
||||
|
|
@ -203,7 +203,6 @@
|
|||
#define MDD_RTC_MONA_IND (MSR_SB_MDD + 0x056)
|
||||
#define MDD_RTC_CENTURY_OFFSET (MSR_SB_MDD + 0x057)
|
||||
|
||||
|
||||
/* ***********************************************************/
|
||||
/* LBUS Device Equates - */
|
||||
/* ***********************************************************/
|
||||
|
|
@ -321,7 +320,6 @@
|
|||
#define GPIOH_30_CLEAR (1 << 30)
|
||||
#define GPIOH_31_CLEAR (1 << 31)
|
||||
|
||||
|
||||
/* GPIO LOW Bank Bit Registers*/
|
||||
#define GPIOL_OUTPUT_VALUE (0x00)
|
||||
#define GPIOL_OUTPUT_ENABLE (0x04)
|
||||
|
|
@ -439,7 +437,6 @@
|
|||
#define PM_AWKD (0x50)
|
||||
#define PM_SSC (0x54)
|
||||
|
||||
|
||||
/* FLASH device macros */
|
||||
#define FLASH_TYPE_NONE 0 /* No flash device installed */
|
||||
#define FLASH_TYPE_NAND 1 /* NAND device */
|
||||
|
|
@ -467,5 +464,4 @@
|
|||
#define FLASH_IO_128B 0x0000FF80
|
||||
#define FLASH_IO_256B 0x0000FF00
|
||||
|
||||
|
||||
#endif /* _CS5536_H */
|
||||
#endif /* _CS5536_H */
|
||||
|
|
|
|||
|
|
@ -33,9 +33,11 @@ static void cs5536_setup_extmsr(void)
|
|||
/* forward MSR access to CS5536_GLINK_PORT_NUM to CS5536_DEV_NUM */
|
||||
msr.hi = msr.lo = 0x00000000;
|
||||
if (CS5536_GLINK_PORT_NUM <= 4) {
|
||||
msr.lo = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
|
||||
msr.lo = CS5536_DEV_NUM <<
|
||||
(unsigned char)((CS5536_GLINK_PORT_NUM - 1) * 8);
|
||||
} else {
|
||||
msr.hi = CS5536_DEV_NUM << (unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
|
||||
msr.hi = CS5536_DEV_NUM <<
|
||||
(unsigned char)((CS5536_GLINK_PORT_NUM - 5) * 8);
|
||||
}
|
||||
wrmsr(GLPCI_ExtMSR, msr);
|
||||
}
|
||||
|
|
@ -92,13 +94,14 @@ static void cs5536_setup_iobase(void)
|
|||
|
||||
static void cs5536_setup_power_button(void)
|
||||
{
|
||||
/* Power Button Setup */
|
||||
/* Power Button Setup */
|
||||
outl(0x40020000, PMS_IO_BASE + 0x40);
|
||||
|
||||
/* setup GPIO24, it is the external signal for 5536 vsb_work_aux
|
||||
; which controls all voltage rails except Vstandby & Vmem.
|
||||
; We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
|
||||
; If GPIO24 is not enabled then soft-off will not work. */
|
||||
* which controls all voltage rails except Vstandby & Vmem.
|
||||
* We need to enable, OUT_AUX1 and OUTPUT_ENABLE in this order.
|
||||
* If GPIO24 is not enabled then soft-off will not work.
|
||||
*/
|
||||
outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUT_AUX1_SELECT);
|
||||
outl(GPIOH_24_SET, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
|
||||
|
||||
|
|
@ -123,18 +126,19 @@ static void cs5536_setup_gpio(void)
|
|||
static void cs5536_disable_internal_uart(void)
|
||||
{
|
||||
msr_t msr;
|
||||
/* ; The UARTs default to enabled.
|
||||
; Disable and reset them and configure them later. (SIO init) */
|
||||
/* The UARTs default to enabled.
|
||||
* Disable and reset them and configure them later. (SIO init)
|
||||
*/
|
||||
msr = rdmsr(MDD_UART1_CONF);
|
||||
msr.lo = 1; // reset
|
||||
msr.lo = 1; // reset
|
||||
wrmsr(MDD_UART1_CONF, msr);
|
||||
msr.lo = 0; // disabled
|
||||
msr.lo = 0; // disabled
|
||||
wrmsr(MDD_UART1_CONF, msr);
|
||||
|
||||
msr = rdmsr(MDD_UART2_CONF);
|
||||
msr.lo = 1; // reset
|
||||
msr.lo = 1; // reset
|
||||
wrmsr(MDD_UART2_CONF, msr);
|
||||
msr.lo = 0; // disabled
|
||||
msr.lo = 0; // disabled
|
||||
wrmsr(MDD_UART2_CONF, msr);
|
||||
}
|
||||
|
||||
|
|
@ -149,7 +153,6 @@ static void cs5536_setup_cis_mode(void)
|
|||
wrmsr(GLPCI_SB_CTRL, msr);
|
||||
}
|
||||
|
||||
|
||||
/* see page 412 of the cs5536 companion book */
|
||||
static void cs5536_setup_onchipuart(void)
|
||||
{
|
||||
|
|
@ -157,11 +160,11 @@ static void cs5536_setup_onchipuart(void)
|
|||
|
||||
/* Setup early for polling only mode.
|
||||
* 1. Eanble GPIO 8 to OUT_AUX1, 9 to IN_AUX1
|
||||
* GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
|
||||
* GPIO LBAR + 0x04, LBAR + 0x10, LBAR + 0x20, LBAR + 34
|
||||
* 2. Enable UART IO space in MDD
|
||||
* MSR 0x51400014 bit 18:16
|
||||
* MSR 0x51400014 bit 18:16
|
||||
* 3. Enable UART controller
|
||||
* MSR 0x5140003A bit 0, 1
|
||||
* MSR 0x5140003A bit 0, 1
|
||||
*/
|
||||
|
||||
/* GPIO8 - UART1_TX */
|
||||
|
|
@ -178,10 +181,10 @@ static void cs5536_setup_onchipuart(void)
|
|||
/* set address to 3F8 */
|
||||
msr = rdmsr(MDD_LEG_IO);
|
||||
msr.lo |= 0x7 << 16;
|
||||
wrmsr(MDD_LEG_IO,msr);
|
||||
wrmsr(MDD_LEG_IO, msr);
|
||||
|
||||
/* Bit 1 = DEVEN (device enable)
|
||||
* Bit 4 = EN_BANKS (allow access to the upper banks
|
||||
/* Bit 1 = DEVEN (device enable)
|
||||
* Bit 4 = EN_BANKS (allow access to the upper banks
|
||||
*/
|
||||
msr.lo = (1 << 4) | (1 << 1);
|
||||
msr.hi = 0;
|
||||
|
|
|
|||
|
|
@ -24,13 +24,12 @@
|
|||
#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
|
||||
#define SMBUS_TIMEOUT (1000)
|
||||
|
||||
|
||||
/* initialization for SMBus Controller */
|
||||
static void cs5536_enable_smbus(void)
|
||||
{
|
||||
|
||||
/* Set SCL freq and enable SMB controller */
|
||||
/*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);*/
|
||||
/*outb((0x20 << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2); */
|
||||
outb((0x7F << 1) | SMB_CTRL2_ENABLE, SMBUS_IO_BASE + SMB_CTRL2);
|
||||
|
||||
/* Setup SMBus host controller address to 0xEF */
|
||||
|
|
@ -43,8 +42,8 @@ static void smbus_delay(void)
|
|||
/* inb(0x80); */
|
||||
}
|
||||
|
||||
|
||||
static int smbus_wait(unsigned smbus_io_base) {
|
||||
static int smbus_wait(unsigned smbus_io_base)
|
||||
{
|
||||
unsigned long loops = SMBUS_TIMEOUT;
|
||||
unsigned char val;
|
||||
|
||||
|
|
@ -54,10 +53,10 @@ static int smbus_wait(unsigned smbus_io_base) {
|
|||
if ((val & SMB_STS_SDAST) != 0)
|
||||
break;
|
||||
if (val & (SMB_STS_BER | SMB_STS_NEGACK)) {
|
||||
/*printk_debug("SMBUS WAIT ERROR %x\n", val);*/
|
||||
/*printk_debug("SMBUS WAIT ERROR %x\n", val); */
|
||||
return SMBUS_ERROR;
|
||||
}
|
||||
} while(--loops);
|
||||
} while (--loops);
|
||||
return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
|
||||
}
|
||||
|
||||
|
|
@ -91,8 +90,8 @@ static int smbus_check_stop_condition(unsigned smbus_io_base)
|
|||
break;
|
||||
}
|
||||
outb((0x7F << 1) | SMB_CTRL2_ENABLE, smbus_io_base + SMB_CTRL2);
|
||||
} while(--loops);
|
||||
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
|
||||
} while (--loops);
|
||||
return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
|
||||
}
|
||||
|
||||
static int smbus_stop_condition(unsigned smbus_io_base)
|
||||
|
|
@ -106,14 +105,15 @@ static int smbus_ack(unsigned smbus_io_base, int state)
|
|||
unsigned char val = inb(smbus_io_base + SMB_CTRL1);
|
||||
|
||||
/* if (state) */
|
||||
outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
|
||||
outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
|
||||
/* else
|
||||
outb(val & ~SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
|
||||
*/
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
|
||||
static int smbus_send_slave_address(unsigned smbus_io_base,
|
||||
unsigned char device)
|
||||
{
|
||||
unsigned char val;
|
||||
|
||||
|
|
@ -122,9 +122,8 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
|
|||
|
||||
/* check for bus conflict and NACK */
|
||||
val = inb(smbus_io_base + SMB_STS);
|
||||
if (((val & SMB_STS_BER) != 0) ||
|
||||
((val & SMB_STS_NEGACK) != 0)) {
|
||||
/* printk_debug("SEND SLAVE ERROR (%x)\n", val);*/
|
||||
if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
|
||||
/* printk_debug("SEND SLAVE ERROR (%x)\n", val); */
|
||||
return SMBUS_ERROR;
|
||||
}
|
||||
return smbus_wait(smbus_io_base);
|
||||
|
|
@ -139,8 +138,7 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
|
|||
|
||||
/* check for bus conflict and NACK */
|
||||
val = inb(smbus_io_base + SMB_STS);
|
||||
if (((val & SMB_STS_BER) != 0) ||
|
||||
((val & SMB_STS_NEGACK) != 0))
|
||||
if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
|
||||
return SMBUS_ERROR;
|
||||
|
||||
return smbus_wait(smbus_io_base);
|
||||
|
|
@ -151,7 +149,9 @@ static unsigned char smbus_get_result(unsigned smbus_io_base)
|
|||
return inb(smbus_io_base + SMB_SDA);
|
||||
}
|
||||
|
||||
static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
|
||||
static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
|
||||
unsigned char device,
|
||||
unsigned char address)
|
||||
{
|
||||
unsigned char error = 0;
|
||||
|
||||
|
|
@ -170,7 +170,7 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char de
|
|||
goto err;
|
||||
}
|
||||
|
||||
smbus_ack(smbus_io_base, 1 );
|
||||
smbus_ack(smbus_io_base, 1);
|
||||
|
||||
if ((smbus_send_command(smbus_io_base, address))) {
|
||||
error = 4;
|
||||
|
|
@ -194,13 +194,12 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char de
|
|||
|
||||
return smbus_get_result(smbus_io_base);
|
||||
|
||||
|
||||
err:
|
||||
err:
|
||||
print_debug("SMBUS READ ERROR:");
|
||||
print_debug_hex8(error);
|
||||
print_debug(" device:");
|
||||
print_debug_hex8(device);
|
||||
print_debug("\r\n");
|
||||
print_debug_hex8(error);
|
||||
print_debug(" device:");
|
||||
print_debug_hex8(device);
|
||||
print_debug("\r\n");
|
||||
/* stop, clean up the error, and leave */
|
||||
smbus_stop_condition(smbus_io_base);
|
||||
outb(inb(smbus_io_base + SMB_STS), smbus_io_base + SMB_STS);
|
||||
|
|
@ -210,6 +209,5 @@ err:
|
|||
|
||||
static inline int smbus_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -25,9 +25,9 @@
|
|||
#include "cs5536.h"
|
||||
|
||||
#define IDE_CFG 0x40
|
||||
#define CHANEN (1L << 1)
|
||||
#define PWB (1L << 14)
|
||||
#define CABLE (1L << 16)
|
||||
#define CHANEN (1L << 1)
|
||||
#define PWB (1L << 14)
|
||||
#define CABLE (1L << 16)
|
||||
#define IDE_DTC 0x48
|
||||
#define IDE_CAST 0x4C
|
||||
#define IDE_ETC 0x50
|
||||
|
|
@ -54,15 +54,15 @@ static void ide_enable(struct device *dev)
|
|||
}
|
||||
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ide_init,
|
||||
.enable = 0,
|
||||
.init = ide_init,
|
||||
.enable = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver ide_driver __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_AMD_CS5536_IDE,
|
||||
};
|
||||
|
|
|
|||
|
|
@ -62,13 +62,13 @@
|
|||
#define SMBUS_TIMEOUT (100*1000*10)
|
||||
#define SMBUS_STATUS_MASK 0xfbff
|
||||
|
||||
|
||||
static void smbus_delay(void)
|
||||
{
|
||||
inb(0x80);
|
||||
}
|
||||
|
||||
static int smbus_wait(unsigned smbus_io_base) {
|
||||
static int smbus_wait(unsigned smbus_io_base)
|
||||
{
|
||||
unsigned long loops = SMBUS_TIMEOUT;
|
||||
unsigned char val;
|
||||
|
||||
|
|
@ -81,13 +81,14 @@ static int smbus_wait(unsigned smbus_io_base) {
|
|||
printk_debug("SMBUS WAIT ERROR %x\n", val);
|
||||
return SMBUS_ERROR;
|
||||
}
|
||||
} while(--loops);
|
||||
} while (--loops);
|
||||
|
||||
outb(0, smbus_io_base + SMB_STS);
|
||||
return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
|
||||
}
|
||||
|
||||
static int smbus_write(unsigned smbus_io_base, unsigned char byte) {
|
||||
static int smbus_write(unsigned smbus_io_base, unsigned char byte)
|
||||
{
|
||||
|
||||
outb(byte, smbus_io_base + SMB_SDA);
|
||||
return smbus_wait(smbus_io_base);
|
||||
|
|
@ -122,17 +123,17 @@ static int smbus_check_stop_condition(unsigned smbus_io_base)
|
|||
if ((val & SMB_CTRL1_STOP) == 0) {
|
||||
break;
|
||||
}
|
||||
} while(--loops);
|
||||
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
|
||||
} while (--loops);
|
||||
return loops ? 0 : SMBUS_WAIT_UNTIL_READY_TIMEOUT;
|
||||
|
||||
/* Make sure everything is cleared and ready to go */
|
||||
|
||||
val = inb(smbus_io_base + SMB_CTRL1);
|
||||
outb(val & ~(SMB_CTRL1_STASTRE | SMB_CTRL1_NMINTE),
|
||||
smbus_io_base + SMB_CTRL1);
|
||||
smbus_io_base + SMB_CTRL1);
|
||||
|
||||
outb(SMB_STS_BER | SMB_STS_NEGACK | SMB_STS_STASTR,
|
||||
smbus_io_base + SMB_STS);
|
||||
smbus_io_base + SMB_STS);
|
||||
|
||||
val = inb(smbus_io_base + SMB_CTRL_STS);
|
||||
outb(val | SMB_CSTS_BB, smbus_io_base + SMB_CTRL_STS);
|
||||
|
|
@ -159,7 +160,8 @@ static int smbus_ack(unsigned smbus_io_base, int state)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
|
||||
static int smbus_send_slave_address(unsigned smbus_io_base,
|
||||
unsigned char device)
|
||||
{
|
||||
unsigned char val;
|
||||
|
||||
|
|
@ -168,8 +170,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
|
|||
|
||||
/* check for bus conflict and NACK */
|
||||
val = inb(smbus_io_base + SMB_STS);
|
||||
if (((val & SMB_STS_BER) != 0) ||
|
||||
((val & SMB_STS_NEGACK) != 0)) {
|
||||
if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0)) {
|
||||
printk_debug("SEND SLAVE ERROR (%x)\n", val);
|
||||
return SMBUS_ERROR;
|
||||
}
|
||||
|
|
@ -178,22 +179,21 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
|
|||
|
||||
static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
|
||||
{
|
||||
unsigned char val;
|
||||
unsigned char val;
|
||||
|
||||
/* send the command */
|
||||
outb(command, smbus_io_base + SMB_SDA);
|
||||
|
||||
/* check for bus conflict and NACK */
|
||||
val = inb(smbus_io_base + SMB_STS);
|
||||
if (((val & SMB_STS_BER) != 0) ||
|
||||
((val & SMB_STS_NEGACK) != 0))
|
||||
if (((val & SMB_STS_BER) != 0) || ((val & SMB_STS_NEGACK) != 0))
|
||||
return SMBUS_ERROR;
|
||||
|
||||
return smbus_wait(smbus_io_base);
|
||||
}
|
||||
|
||||
static void _doread(unsigned smbus_io_base, unsigned char device,
|
||||
unsigned char address, unsigned char *data, int count)
|
||||
unsigned char address, unsigned char *data, int count)
|
||||
{
|
||||
int ret;
|
||||
int index = 0;
|
||||
|
|
@ -207,7 +207,7 @@ static void _doread(unsigned smbus_io_base, unsigned char device,
|
|||
if ((ret = smbus_start_condition(smbus_io_base)))
|
||||
goto err;
|
||||
|
||||
index++; /* 2 */
|
||||
index++; /* 2 */
|
||||
if ((ret = smbus_send_slave_address(smbus_io_base, device)))
|
||||
goto err;
|
||||
|
||||
|
|
@ -226,7 +226,7 @@ static void _doread(unsigned smbus_io_base, unsigned char device,
|
|||
if ((ret = smbus_send_slave_address(smbus_io_base, device | 0x01)))
|
||||
goto err;
|
||||
|
||||
while(count) {
|
||||
while (count) {
|
||||
/* Set the ACK if this is the next to last byte */
|
||||
smbus_ack(smbus_io_base, (count == 2) ? 1 : 0);
|
||||
|
||||
|
|
@ -249,12 +249,12 @@ static void _doread(unsigned smbus_io_base, unsigned char device,
|
|||
|
||||
return;
|
||||
|
||||
err:
|
||||
err:
|
||||
printk_debug("SMBUS READ ERROR (%d): %d\n", index, ret);
|
||||
}
|
||||
|
||||
static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
|
||||
unsigned char device,
|
||||
unsigned char device,
|
||||
unsigned char address)
|
||||
{
|
||||
unsigned char val = 0;
|
||||
|
|
@ -263,16 +263,18 @@ static unsigned char do_smbus_read_byte(unsigned smbus_io_base,
|
|||
}
|
||||
|
||||
static unsigned short do_smbus_read_word(unsigned smbus_io_base,
|
||||
unsigned char device, unsigned char address)
|
||||
unsigned char device,
|
||||
unsigned char address)
|
||||
{
|
||||
unsigned short val = 0;
|
||||
_doread(smbus_io_base, device, address, (unsigned char *) &val,
|
||||
sizeof(val));
|
||||
_doread(smbus_io_base, device, address, (unsigned char *)&val,
|
||||
sizeof(val));
|
||||
return val;
|
||||
}
|
||||
|
||||
static int _dowrite(unsigned smbus_io_base, unsigned char device,
|
||||
unsigned char address, unsigned char *data, int count) {
|
||||
unsigned char address, unsigned char *data, int count)
|
||||
{
|
||||
|
||||
int ret;
|
||||
|
||||
|
|
@ -288,7 +290,7 @@ static int _dowrite(unsigned smbus_io_base, unsigned char device,
|
|||
if ((ret = smbus_send_command(smbus_io_base, address)))
|
||||
goto err;
|
||||
|
||||
while(count) {
|
||||
while (count) {
|
||||
if ((ret = smbus_write(smbus_io_base, *data++)))
|
||||
goto err;
|
||||
count--;
|
||||
|
|
@ -297,21 +299,21 @@ static int _dowrite(unsigned smbus_io_base, unsigned char device,
|
|||
smbus_stop_condition(smbus_io_base);
|
||||
return 0;
|
||||
|
||||
err:
|
||||
err:
|
||||
printk_debug("SMBUS WRITE ERROR: %d\n", ret);
|
||||
return -1;
|
||||
}
|
||||
|
||||
|
||||
static int do_smbus_write_byte(unsigned smbus_io_base, unsigned char device,
|
||||
unsigned char address, unsigned char data)
|
||||
unsigned char address, unsigned char data)
|
||||
{
|
||||
return _dowrite(smbus_io_base, device, address,
|
||||
(unsigned char *) &data, 1);
|
||||
(unsigned char *)&data, 1);
|
||||
}
|
||||
|
||||
static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device, unsigned char address,
|
||||
unsigned short data)
|
||||
static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device,
|
||||
unsigned char address, unsigned short data)
|
||||
{
|
||||
return _dowrite(smbus_io_base, device ,address, (unsigned char *) &data, 2);
|
||||
return _dowrite(smbus_io_base, device, address, (unsigned char *)&data,
|
||||
2);
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue