mb/supermicro/x11-lga1151-series: correct superio interrupts

Add interrupts for all enabled superio devices to quiet the warning
about missing interrupts in devicetree.

Vendor uses interrupt 0x00 for all devices except SUART* and KBC, so
let's do that, too. This also changes SWC from 0x0b to 0x00.

Verified with superiotool on X11SSM-F.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7a6dc7345f020e53415a7d0d104ce93ab4b194fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonas Löffelholz
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michael Niewöhner 2020-07-25 23:47:44 +02:00 committed by Michael Niewöhner
parent 71a22e3cfc
commit 2a28c81614
2 changed files with 14 additions and 6 deletions

View File

@ -112,13 +112,17 @@ chip soc/intel/skylake
io 0x62 = 0xa10
io 0x64 = 0xa20
io 0x66 = 0xa30
irq 0x70 = 0xb
irq 0x70 = 0x00
end
device pnp 2e.5 off end # KBC
device pnp 2e.7 on end # GPIO
device pnp 2e.7 on # GPIO
irq 0x70 = 0x00
end
device pnp 2e.b off end # SUART3
device pnp 2e.c off end # SUART4
device pnp 2e.d on end # iLPC2AHB
device pnp 2e.d on # iLPC2AHB
irq 0x70 = 0x00
end
device pnp 2e.e on # Mailbox
io 0x60 = 0xa40
irq 0x70 = 0x00

View File

@ -99,13 +99,17 @@ chip soc/intel/skylake
io 0x62 = 0xa10
io 0x64 = 0xa20
io 0x66 = 0xa30
irq 0x70 = 0xb
irq 0x70 = 0x00
end
device pnp 2e.5 off end # KBC
device pnp 2e.7 on end # GPIO
device pnp 2e.7 on # GPIO
irq 0x70 = 0x00
end
device pnp 2e.b off end # SUART3
device pnp 2e.c off end # SUART4
device pnp 2e.d on end # iLPC2AHB
device pnp 2e.d on # iLPC2AHB
irq 0x70 = 0x00
end
device pnp 2e.e on # Mailbox
io 0x60 = 0xa40
irq 0x70 = 0x00