mb/google/dedede: Enable AP <-> H1 Communication

Turn on the H1 device in the devicetree. Configure the concerned GPIOs
and enable the required config items.

BUG=None
TEST=Build the mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I37972635454cd0d35608623e7be4110012ace658
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Karthikeyan Ramasubramanian 2020-02-06 17:58:07 -07:00 committed by Patrick Georgi
parent 47607bdc83
commit 2a3cef29d8
3 changed files with 57 additions and 4 deletions

View File

@ -1,11 +1,14 @@
config BOARD_GOOGLE_BASEBOARD_DEDEDE config BOARD_GOOGLE_BASEBOARD_DEDEDE
def_bool n def_bool n
select DRIVERS_SPI_ACPI
select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_ESPI select EC_GOOGLE_CHROMEEC_ESPI
select HAVE_ACPI_RESUME select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES select HAVE_ACPI_TABLES
select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_HAS_SPI_TPM_CR50
select MAINBOARD_HAS_TPM2
select SOC_INTEL_JASPERLAKE select SOC_INTEL_JASPERLAKE
if BOARD_GOOGLE_BASEBOARD_DEDEDE if BOARD_GOOGLE_BASEBOARD_DEDEDE
@ -25,6 +28,9 @@ config DEVICETREE
string string
default "variants/baseboard/devicetree.cb" default "variants/baseboard/devicetree.cb"
config DRIVER_TPM_SPI_BUS
default 0x1
config MAINBOARD_DIR config MAINBOARD_DIR
string string
default "google/dedede" default "google/dedede"
@ -41,6 +47,10 @@ config MAX_CPUS
int int
default 4 default 4
config TPM_TIS_ACPI_INTERRUPT
int
default 4 # GPE0_DW0_4 (GPP_B4)
config UART_FOR_CONSOLE config UART_FOR_CONSOLE
int int
default 2 default 2

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@ -29,13 +29,13 @@ chip soc/intel/tigerlake
}" }"
register "SerialIoGSpiMode" = "{ register "SerialIoGSpiMode" = "{
[PchSerialIoIndexGSPI0] = PchSerialIoDisabled, [PchSerialIoIndexGSPI0] = PchSerialIoPci,
[PchSerialIoIndexGSPI1] = PchSerialIoDisabled, [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
[PchSerialIoIndexGSPI2] = PchSerialIoDisabled, [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
}" }"
register "SerialIoGSpiCsMode" = "{ register "SerialIoGSpiCsMode" = "{
[PchSerialIoIndexGSPI0] = 0, [PchSerialIoIndexGSPI0] = 1,
[PchSerialIoIndexGSPI1] = 0, [PchSerialIoIndexGSPI1] = 0,
[PchSerialIoIndexGSPI2] = 0, [PchSerialIoIndexGSPI2] = 0,
}" }"
@ -52,6 +52,22 @@ chip soc/intel/tigerlake
[PchSerialIoIndexUART2] = PchSerialIoDisabled, [PchSerialIoIndexUART2] = PchSerialIoDisabled,
}" }"
# Intel Common SoC Config
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
#| GSPI0 | cr50 TPM. Early init is |
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
#+-------------------+---------------------------+
register "common_soc_config" = "{
.gspi[0] = {
.speed_mhz = 1,
.early_init = 1,
},
}"
device domain 0 on device domain 0 on
device pci 00.0 off end # Host Bridge device pci 00.0 off end # Host Bridge
device pci 02.0 off end # Integrated Graphics Device device pci 02.0 off end # Integrated Graphics Device
@ -87,7 +103,14 @@ chip soc/intel/tigerlake
device pci 1c.7 off end # PCI Express Root Port 8 device pci 1c.7 off end # PCI Express Root Port 8
device pci 1e.0 off end # UART 0 device pci 1e.0 off end # UART 0
device pci 1e.1 off end # UART 1 device pci 1e.1 off end # UART 1
device pci 1e.2 off end # GSPI 0 device pci 1e.2 on
chip drivers/spi/acpi
register "hid" = "ACPI_DT_NAMESPACE_HID"
register "compat_string" = ""google,cr50""
register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)"
device spi 0 on end
end
end # GSPI 0
device pci 1e.3 off end # GSPI 1 device pci 1e.3 off end # GSPI 1
device pci 1f.0 on device pci 1f.0 on
chip ec/google/chromeec chip ec/google/chromeec

View File

@ -21,11 +21,31 @@ static const struct pad_config gpio_table[] = {
/* A4 : ESPI_CS# */ /* A4 : ESPI_CS# */
/* A5 : ESPI_CLK */ /* A5 : ESPI_CLK */
/* A6 : ESPI_RESET_L */ /* A6 : ESPI_RESET_L */
/* B4 : H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT),
/* B15 : H1_SLAVE_SPI_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : H1_SLAVE_SPI_CLK */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
/* B17 : H1_SLAVE_SPI_MISO_R */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
}; };
/* Early pad configuration in bootblock */ /* Early pad configuration in bootblock */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
/* ToDo: Fill early gpio configuration */ /* B4 : H1_PCH_INT_ODL */
PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT),
/* B15 : H1_SLAVE_SPI_CS_L */
PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
/* B16 : H1_SLAVE_SPI_CLK */
PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
/* B17 : H1_SLAVE_SPI_MISO_R */
PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
/* B18 : H1_SLAVE_SPI_MOSI_R */
PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
}; };
const struct pad_config *__weak variant_gpio_table(size_t *num) const struct pad_config *__weak variant_gpio_table(size_t *num)