mb/google/dedede: Enable AP <-> H1 Communication
Turn on the H1 device in the devicetree. Configure the concerned GPIOs and enable the required config items. BUG=None TEST=Build the mainboard. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I37972635454cd0d35608623e7be4110012ace658 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38772 Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -1,11 +1,14 @@
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config BOARD_GOOGLE_BASEBOARD_DEDEDE
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def_bool n
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select DRIVERS_SPI_ACPI
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select EC_GOOGLE_CHROMEEC
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select EC_GOOGLE_CHROMEEC_BOARDID
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select EC_GOOGLE_CHROMEEC_ESPI
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select MAINBOARD_HAS_CHROMEOS
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select MAINBOARD_HAS_SPI_TPM_CR50
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select MAINBOARD_HAS_TPM2
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select SOC_INTEL_JASPERLAKE
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if BOARD_GOOGLE_BASEBOARD_DEDEDE
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@ -25,6 +28,9 @@ config DEVICETREE
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string
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default "variants/baseboard/devicetree.cb"
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config DRIVER_TPM_SPI_BUS
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default 0x1
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config MAINBOARD_DIR
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string
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default "google/dedede"
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@ -41,6 +47,10 @@ config MAX_CPUS
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int
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default 4
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config TPM_TIS_ACPI_INTERRUPT
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int
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default 4 # GPE0_DW0_4 (GPP_B4)
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config UART_FOR_CONSOLE
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int
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default 2
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@ -29,13 +29,13 @@ chip soc/intel/tigerlake
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}"
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register "SerialIoGSpiMode" = "{
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[PchSerialIoIndexGSPI0] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI0] = PchSerialIoPci,
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[PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
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[PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
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}"
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register "SerialIoGSpiCsMode" = "{
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[PchSerialIoIndexGSPI0] = 0,
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[PchSerialIoIndexGSPI0] = 1,
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[PchSerialIoIndexGSPI1] = 0,
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[PchSerialIoIndexGSPI2] = 0,
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}"
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@ -52,6 +52,22 @@ chip soc/intel/tigerlake
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[PchSerialIoIndexUART2] = PchSerialIoDisabled,
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}"
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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}"
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device domain 0 on
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device pci 00.0 off end # Host Bridge
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device pci 02.0 off end # Integrated Graphics Device
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@ -87,7 +103,14 @@ chip soc/intel/tigerlake
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device pci 1c.7 off end # PCI Express Root Port 8
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device pci 1e.0 off end # UART 0
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device pci 1e.1 off end # UART 1
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device pci 1e.2 off end # GSPI 0
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device pci 1e.2 on
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chip drivers/spi/acpi
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register "hid" = "ACPI_DT_NAMESPACE_HID"
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register "compat_string" = ""google,cr50""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)"
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device spi 0 on end
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end
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end # GSPI 0
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device pci 1e.3 off end # GSPI 1
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device pci 1f.0 on
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chip ec/google/chromeec
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@ -21,11 +21,31 @@ static const struct pad_config gpio_table[] = {
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/* A4 : ESPI_CS# */
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/* A5 : ESPI_CLK */
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/* A6 : ESPI_RESET_L */
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/* B4 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT),
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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};
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/* Early pad configuration in bootblock */
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static const struct pad_config early_gpio_table[] = {
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/* ToDo: Fill early gpio configuration */
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/* B4 : H1_PCH_INT_ODL */
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PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT),
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/* B15 : H1_SLAVE_SPI_CS_L */
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PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
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/* B16 : H1_SLAVE_SPI_CLK */
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PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
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/* B17 : H1_SLAVE_SPI_MISO_R */
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PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
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/* B18 : H1_SLAVE_SPI_MOSI_R */
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PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
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};
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const struct pad_config *__weak variant_gpio_table(size_t *num)
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