diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb
index ac3a5c1da2..bb925cebe1 100644
--- a/src/mainboard/google/chell/devicetree.cb
+++ b/src/mainboard/google/chell/devicetree.cb
@@ -16,6 +16,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb
index 894f0e1858..89fcff8ccd 100644
--- a/src/mainboard/google/glados/devicetree.cb
+++ b/src/mainboard/google/glados/devicetree.cb
@@ -16,6 +16,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb
index cf3649aa4d..50b3e1e8dc 100644
--- a/src/mainboard/google/lars/devicetree.cb
+++ b/src/mainboard/google/lars/devicetree.cb
@@ -15,6 +15,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable DPTF
 	register "dptf_enable" = "1"
 
diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb
index d2a70c8711..62a0c26e56 100644
--- a/src/mainboard/intel/kunimitsu/devicetree.cb
+++ b/src/mainboard/intel/kunimitsu/devicetree.cb
@@ -15,6 +15,9 @@ chip soc/intel/skylake
 	# EC host command range is in 0x800-0x8ff
 	register "gen1_dec" = "0x00fc0801"
 
+	# Enable "Intel Speed Shift Technology"
+	register "speed_shift_enable" = "1"
+
 	# Enable DPTF
 	register "dptf_enable" = "1"