From 2a6a79c70657435880be7f00e48debdd559b91b5 Mon Sep 17 00:00:00 2001 From: Ruihai Zhou Date: Thu, 7 Sep 2023 19:10:54 +0800 Subject: [PATCH] drivers/mipi: sta_himax83102: Completely pull GPW to VGL before TP term The sta_himax83102 panel sometimes shows abnormally flickering horizontal lines. The front gate output will precharge the X point of the next pole circuit before TP term starts, and wait until the end of the TP term to resume the CLK. For this reason, the X point must be maintained during the TP term. In abnormal case, we measured a slight leakage at point X. This is because during the TP term, the GPW does not fully pull the VGL low, causing the TFT to not be closed tightly. To fix this, we completely pull GPW to VGL before entering the TP term. This will ensure that the TFT is closed tightly and prevent the abnormal display. BUG=b:299249186 BRANCH=corsola TEST=FW Screen display normally Signed-off-by: Ruihai Zhou Change-Id: I5dddaaa38917a65990c1474b657db5eb551940b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77692 Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) --- src/drivers/mipi/panel-STA_HIMAX83102_J02.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/drivers/mipi/panel-STA_HIMAX83102_J02.c b/src/drivers/mipi/panel-STA_HIMAX83102_J02.c index e5a8fb5f72..01fa6f55cf 100644 --- a/src/drivers/mipi/panel-STA_HIMAX83102_J02.c +++ b/src/drivers/mipi/panel-STA_HIMAX83102_J02.c @@ -78,9 +78,8 @@ struct panel_serializable_data STA_HIMAX83102_J02 = { PANEL_DCS(0xB1, 0x01, 0xBF, 0x11), PANEL_DCS(0xCB, 0x86), PANEL_DCS(0xD2, 0x3C, 0xFA), - PANEL_DCS(0xE9, 0xC5), - PANEL_DCS(0xD3, 0x00, 0x00, 0x00, 0x00, 0x80, 0x0C, 0x01), - PANEL_DCS(0xE9, 0x3F), + PANEL_DCS(0xD3, 0x00, 0x00, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, + 0x0C, 0x01), PANEL_DCS(0xE7, 0x02, 0x00, 0x28, 0x01, 0x7E, 0x0F, 0x7E, 0x10, 0xA0, 0x00, 0x00, 0x20, 0x40, 0x50, 0x40), PANEL_DCS(0xBD, 0x02),