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soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars 

BAR address used during early initilization of GPSI 2 is overlapping with UART bar.

//For GSPI2 this is the address calculated
GSPI_BUS_BASE(0xFE030000,2)=0xFE032000
GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB)

//overlaps with
CONSOLE_UART_BASE_ADDRESS -> 0xfe032000

TEST=none

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Bora Guvendik 2020-11-16 11:23:48 -08:00 committed by Patrick Georgi
parent c3c3e453ff
commit 2a70419e7c
1 changed files with 1 additions and 1 deletions
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2
src/soc/intel/alderlake/Kconfig
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@ -159,7 +159,7 @@ config SOC_INTEL_UART_DEV_MAX
config CONSOLE_UART_BASE_ADDRESS
hex
default 0xfe032000
default 0xfe03e000
depends on INTEL_LPSS_UART_FOR_CONSOLE
# Clock divider parameters for 115200 baud rate