Adds a CONFIG_MAX_PCI_BUSES to pci_locate_device()

Default is 255.

This allows mainboard configs for working across various groups
of boards that differ a device that may not loaded.

If you search for a device that is not loaded and max buses is 255
then there can be up to a 8 second delay to search the entire PCI space.
Board configs that know thier max bus can limit this search space.


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2273 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Richard Smith 2006-04-23 23:12:21 +00:00
parent 2f19800268
commit 2a7352cb9d
3 changed files with 16 additions and 1 deletions

View File

@ -168,7 +168,7 @@ static inline __attribute__((always_inline)) void pci_write_config32(device_t de
#define PCI_DEV_INVALID (0xffffffffU)
static device_t pci_locate_device(unsigned pci_id, device_t dev)
{
for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
for(; dev <= PCI_DEV(CONFIG_MAX_PCI_BUSES, 31, 7); dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
if (id == pci_id) {

View File

@ -490,6 +490,11 @@ define CONFIG_SYS_CLK_FREQ
export used
comment "System clock frequency in MHz"
end
define CONFIG_MAX_PCI_BUSES
default 255
export always
comment "Maximum number of PCI buses to search for devices"
end
###############################################
# SMP options
###############################################

View File

@ -38,6 +38,7 @@ uses CONFIG_CONSOLE_SERIAL8250
uses CONFIG_UDELAY_TSC
uses CONFIG_PCI_ROM_RUN
uses CONFIG_CONSOLE_VGA
uses CONFIG_MAX_PCI_BUSES
## ROM_SIZE is the size of boot ROM that this board will use.
default ROM_SIZE = 256*1024
@ -121,5 +122,14 @@ default CROSS_COMPILE=""
default CC="$(CROSS_COMPILE)gcc -m32"
default HOSTCC="gcc"
##
## Set this to the max PCI bus number you
## would ever use for PCI config IO.
## Setting this number very high will make
## pci_locate_device take a long time when
## it can't find a device.
##
default CONFIG_MAX_PCI_BUSES = 5
end