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sb/intel/gpio: Cache gpiobase in ramstage and romstage 

Implement caching like it's done with pmbase.

Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27664
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph 2018-07-27 09:49:14 +02:00 committed by Felix Held
parent 030ba1bff3
commit 2a7be5bf30
2 changed files with 22 additions and 9 deletions
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26
src/southbridge/intel/common/gpio.c
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@ -18,18 +18,36 @@
#include <arch/io.h>
#include <device/device.h>
#include <device/pci.h>
#include <arch/early_variables.h>
#include "gpio.h"
#define MAX_GPIO_NUMBER 75 /* zero based */
/* LPC GPIO Base Address Register */
#define GPIO_BASE 0x48
/* PCI Configuration Space (D31:F0): LPC */
#if defined(__SIMPLE_DEVICE__)
#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
#else
#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0))
#endif
static u16 get_gpio_base(void)
{
#if defined(__PRE_RAM__) || defined(__SMM__)
return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
#if defined(__SMM__)
/* Don't assume GPIO_BASE is still the same */
return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
#else
return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
GPIO_BASE) & 0xfffc;
static u16 gpiobase CAR_GLOBAL;
if (gpiobase)
return gpiobase;
gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
return gpiobase;
#endif
}

5
src/southbridge/intel/common/gpio.h
View File

@ -19,11 +19,6 @@
#include <stdint.h>
#include <compiler.h>
/* LPC GPIO Base Address Register */
#define GPIO_BASE 0x48
/* PCI Configuration Space (D31:F0): LPC */
#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
/* ICH7 GPIOBASE */
#define GPIO_USE_SEL 0x00
#define GP_IO_SEL 0x04