sb/intel/gpio: Cache gpiobase in ramstage and romstage
Implement caching like it's done with pmbase. Change-Id: I26d56a9ff1a8d6e64c164f36e23b846b8b459380 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27664 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -18,18 +18,36 @@
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#include <arch/io.h>
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#include <arch/io.h>
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#include <device/device.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci.h>
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#include <arch/early_variables.h>
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#include "gpio.h"
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#include "gpio.h"
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#define MAX_GPIO_NUMBER 75 /* zero based */
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#define MAX_GPIO_NUMBER 75 /* zero based */
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/* LPC GPIO Base Address Register */
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#define GPIO_BASE 0x48
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/* PCI Configuration Space (D31:F0): LPC */
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#if defined(__SIMPLE_DEVICE__)
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#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
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#else
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#define PCH_LPC_DEV dev_find_slot(0, PCI_DEVFN(0x1f, 0))
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#endif
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static u16 get_gpio_base(void)
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static u16 get_gpio_base(void)
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{
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{
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#if defined(__PRE_RAM__) || defined(__SMM__)
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#if defined(__SMM__)
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return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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/* Don't assume GPIO_BASE is still the same */
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return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
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#else
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#else
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return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
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static u16 gpiobase CAR_GLOBAL;
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GPIO_BASE) & 0xfffc;
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if (gpiobase)
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return gpiobase;
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gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffe;
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return gpiobase;
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#endif
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#endif
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}
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}
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@ -19,11 +19,6 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <compiler.h>
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#include <compiler.h>
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/* LPC GPIO Base Address Register */
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#define GPIO_BASE 0x48
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/* PCI Configuration Space (D31:F0): LPC */
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#define PCH_LPC_DEV PCI_DEV(0, 0x1f, 0)
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/* ICH7 GPIOBASE */
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/* ICH7 GPIOBASE */
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#define GPIO_USE_SEL 0x00
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#define GPIO_USE_SEL 0x00
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#define GP_IO_SEL 0x04
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#define GP_IO_SEL 0x04
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