nb/intel/x4x/iomap.h: Rename to memmap.h

It primarily contains definitions for MMIO windows. Also, remove
includes from files not directly using the definitions it contains.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.

Change-Id: Id28080d9b2924463dd3720492d5e717d65fa0071
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45419
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/northbridge/intel/x4x/acpi/x4x.asl

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include "hostbridge.asl"
-#include "../iomap.h"
+#include "../memmap.h"
 #include <southbridge/intel/common/rcba.h>
 
 /* PCI Device Resource Consumption */

src/northbridge/intel/x4x/bootblock.c

@@ -5,7 +5,6 @@
 #include <device/pci_ops.h>
 
 #include "x4x.h"
-#include "iomap.h"
 
 void bootblock_early_northbridge_init(void)
 {

src/northbridge/intel/x4x/dq_dqs.c

@@ -6,7 +6,6 @@
 #include <string.h>
 #include <types.h>
 #include "x4x.h"
-#include "iomap.h"
 
 static void print_dll_setting(const struct dll_setting *dll_setting,
 			u8 default_verbose)

src/northbridge/intel/x4x/early_init.c

@@ -2,7 +2,6 @@
 
 #include <stdint.h>
 #include <device/pci_ops.h>
-#include "iomap.h"
 #if CONFIG(SOUTHBRIDGE_INTEL_I82801GX)
 #include <southbridge/intel/i82801gx/i82801gx.h> /* DEFAULT_PMBASE */
 #else

src/northbridge/intel/x4x/memmap.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-or-later */
 
-#ifndef X4X_IOMAP_H
-#define X4X_IOMAP_H
+#ifndef X4X_MEMMAP_H
+#define X4X_MEMMAP_H
 
 #define DEFAULT_MCHBAR		0xfed14000	/* 16 KB */
 #define DEFAULT_DMIBAR		0xfed18000	/* 4 KB */
@@ -10,4 +10,4 @@
 
 #define TPM_BASE_ADDRESS	0xfed40000
 
-#endif /* X4X_IOMAP_H */
+#endif /* X4X_MEMMAP_H */

src/northbridge/intel/x4x/northbridge.c

@@ -8,7 +8,7 @@
 #include <device/device.h>
 #include <boot/tables.h>
 #include <acpi/acpi.h>
-#include <northbridge/intel/x4x/iomap.h>
+#include <northbridge/intel/x4x/memmap.h>
 #include <northbridge/intel/x4x/chip.h>
 #include <northbridge/intel/x4x/x4x.h>
 #include <cpu/intel/smm_reloc.h>

src/northbridge/intel/x4x/raminit.c

@@ -14,7 +14,6 @@
 #include <timestamp.h>
 #include <types.h>
 
-#include "iomap.h"
 #include "x4x.h"
 
 #define MRC_CACHE_VERSION 0

src/northbridge/intel/x4x/raminit_ddr23.c

@@ -13,7 +13,6 @@
 #include <southbridge/intel/i82801jx/i82801jx.h>
 #endif
 #include <string.h>
-#include "iomap.h"
 #include "x4x.h"
 
 #define ME_UMA_SIZEMB 0

src/northbridge/intel/x4x/rcven.c

@@ -3,7 +3,6 @@
 #include <device/mmio.h>
 #include <console/console.h>
 #include <delay.h>
-#include "iomap.h"
 #include "x4x.h"
 
 #define MAX_COARSE 15

src/northbridge/intel/x4x/x4x.h

@@ -4,7 +4,7 @@
 #define __NORTHBRIDGE_INTEL_X4X_H__
 
 #include <stdint.h>
-#include "iomap.h"
+#include "memmap.h"
 
 /*
  * D0:F0