Add GPIO dumping utility for Intel ICH series southbridges.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Signed-off-by: Joseph Smith <joe@smittys.pointclark.net> Acked-by: Ronald G. Minnich <rminnich@gmail.com> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3132 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Carl-Daniel Hailfinger
parent
0719b8e460
commit
2aa1436777
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#
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# Makefile for ich_gpio utility
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#
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# (C) 2008 by coresystems GmbH
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# written by Stefan Reinauer <stepan@coresystems.de>
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# Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
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#
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PROGRAM = ich_gpio
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CC = gcc
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STRIP = strip
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INSTALL = /usr/bin/install
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PREFIX = /usr/local
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CFLAGS = -O2 -g -Wall
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OS_ARCH = $(shell uname)
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ifeq ($(OS_ARCH), SunOS)
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LDFLAGS = -lpci -lz
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else
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LDFLAGS = -lpci -lz -static
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STRIP_ARGS = -s
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endif
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OBJS = ich_gpio.o
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all: pciutils dep $(PROGRAM)
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$(PROGRAM): $(OBJS)
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$(CC) -o $(PROGRAM) $(OBJS) $(LDFLAGS)
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$(STRIP) $(STRIP_ARGS) $(PROGRAM)
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clean:
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rm -f *.o *~
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distclean: clean
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rm -f $(PROGRAM) .dependencies
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dep:
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@$(CC) -MM *.c > .dependencies
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pciutils:
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@echo; echo -n "Checking for pciutils and zlib... "
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@$(shell ( echo "#include <pci/pci.h>"; \
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echo "struct pci_access *pacc;"; \
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echo "int main(int argc, char **argv)"; \
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echo "{ pacc = pci_alloc(); return 0; }"; ) > .test.c )
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@$(CC) $(CFLAGS) .test.c -o .test $(LDFLAGS) &>/dev/null && \
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echo "found." || ( echo "not found."; echo; \
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echo "Please install pciutils-devel and zlib-devel."; \
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echo "See README for more information."; echo; \
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rm -f .test.c .test; exit 1)
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@rm -f .test.c .test
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install: $(PROGRAM)
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$(INSTALL) $(PROGRAM) $(PREFIX)/sbin
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mkdir -p $(PREFIX)/share/man/man8
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$(INSTALL) $(PROGRAM).8 $(PREFIX)/share/man/man8
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.PHONY: all clean distclean dep pciutils
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-include .dependencies
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.TH ICH_GPIO 8 "March 8, 2008"
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.SH NAME
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ich_gpio \- Intel southbridge GPIO Dump Utility
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.SH SYNOPSIS
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.B ich_gpio
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.SH DESCRIPTION
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.B ich_gpio
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is a user-space utility which can dump all
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register contents of the Intel ICH series Southbridges.
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.PP
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It is mainly used for coreboot development purposes (see coreboot.org
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for details on coreboot), but it may also be useful for other things.
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.PP
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Here is an example output:
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.br
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[root@localhost dumpgpio]# ich_gpio
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.br
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Intel Southbridge: 8086:24c0
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.br
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GPIOBASE = 0x0500
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.br
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gpiobase+0x0000: 0x1a003180
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.br
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gpiobase+0x0004: 0x0900ffff
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.br
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gpiobase+0x0008: 0x00000000
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.br
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gpiobase+0x000c: 0x1bbf0000
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.br
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gpiobase+0x0010: 0x00000000
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.br
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gpiobase+0x0014: 0x00000000
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.br
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gpiobase+0x0018: 0x00040000
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.br
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gpiobase+0x001c: 0x00000000
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.br
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gpiobase+0x0020: 0x00000000
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.br
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gpiobase+0x0024: 0x00000000
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.br
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gpiobase+0x0028: 0x00000000
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.br
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gpiobase+0x002c: 0x00003000
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.br
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gpiobase+0x0030: 0x00000fff
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.br
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gpiobase+0x0034: 0x00000e00
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.br
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gpiobase+0x0038: 0x00000fff
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.br
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gpiobase+0x003c: 0x00000000
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.PP
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Please consult your datasheet for the register meanings.
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.SH OPTIONS
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No command line options needed just run ich_gpio.
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.SH AUTHORS
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Please see the individual source code files.
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@ -0,0 +1,91 @@
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/*
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* dump gpio on intel ICH series southbridges
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*
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* Copyright (C) 2008 by coresystems GmbH
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* written by Stefan Reinauer <stepan@coresystems.de>
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* Copyright (C) 2008 Joseph Smith <joe@smittys.pointclark.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <errno.h>
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#include <fcntl.h>
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#include <sys/mman.h>
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#include <unistd.h>
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#include <stdio.h>
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#include <string.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <getopt.h>
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#include <sys/io.h>
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#include <pci/pci.h>
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int map_gpio(uint16_t gpio)
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{
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int i;
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unsigned long size=0x40;
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for (i=0; i<size; i+=4) {
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printf("gpiobase+0x%04x: 0x%08x\n", i, inl(gpio+i));
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}
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return 0;
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}
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int main(int argc, char *argv[])
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{
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struct pci_access *pacc;
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struct pci_dev *sb;
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uint16_t gpiobadd;
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uint16_t device;
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if (iopl(3)) {
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perror("You need to be root.\n");
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exit(1);
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}
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pacc = pci_alloc();
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pci_init(pacc);
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pci_scan_bus(pacc);
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sb = pci_get_dev(pacc, 0, 0, 0x1f, 0);
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if (!sb) {
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printf("No southbridge found.\n");
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exit(1);
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}
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if (pci_read_word(sb, 0) != 0x8086) {
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printf("Not an Intel southbridge.\n");
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exit(1);
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}
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printf("Intel Southbridge: %04x:%04x\n",
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pci_read_word(sb, 0), pci_read_word(sb, 2));
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device = pci_read_word(sb, 2);
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if (device < 0x2640) {
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gpiobadd = pci_read_word(sb, 0x58) & 0xfffc;
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} else if (device >= 0x2640) {
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gpiobadd = pci_read_word(sb, 0x48) & 0xfffc;
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}
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printf("GPIOBASE = 0x%04x\n\n", gpiobadd);
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map_gpio(gpiobadd);
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return 0;
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}
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