haswell/lynxpoint: Align cosmetics with Broadwell
Tested with BUILD_TIMELESS=1, Google Wolf does not change. Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
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@ -65,50 +65,6 @@ static void generate_cstate_entries(acpi_cstate_t *cstates,
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acpigen_pop_len();
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}
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static void generate_C_state_entries(void)
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{
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struct cpu_info *info;
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struct cpu_driver *cpu;
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struct device *lapic;
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struct cpu_intel_haswell_config *conf = NULL;
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/* Find the SpeedStep CPU in the device tree using magic APIC ID */
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lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
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if (!lapic)
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return;
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conf = lapic->chip_info;
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if (!conf)
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return;
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/* Find CPU map of supported C-states */
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info = cpu_info();
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if (!info)
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return;
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cpu = find_cpu_driver(info->cpu);
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if (!cpu || !cpu->cstates)
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return;
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acpigen_emit_byte(0x14); /* MethodOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("_CST");
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acpigen_emit_byte(0x00); /* No Arguments */
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/* If running on AC power */
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acpigen_emit_byte(0xa0); /* IfOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("PWRS");
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acpigen_emit_byte(0xa4); /* ReturnOp */
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generate_cstate_entries(cpu->cstates, conf->c1_acpower,
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conf->c2_acpower, conf->c3_acpower);
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acpigen_pop_len();
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/* Else on battery power */
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acpigen_emit_byte(0xa4); /* ReturnOp */
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generate_cstate_entries(cpu->cstates, conf->c1_battery,
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conf->c2_battery, conf->c3_battery);
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acpigen_pop_len();
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}
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static acpi_tstate_t tss_table_fine[] = {
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{ 100, 1000, 0, 0x00, 0 },
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{ 94, 940, 0, 0x1f, 0 },
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@ -161,6 +117,50 @@ static void generate_T_state_entries(int core, int cores_per_package)
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ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
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}
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static void generate_C_state_entries(void)
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{
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struct cpu_info *info;
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struct cpu_driver *cpu;
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struct device *lapic;
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struct cpu_intel_haswell_config *conf = NULL;
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/* Find the SpeedStep CPU in the device tree using magic APIC ID */
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lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
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if (!lapic)
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return;
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conf = lapic->chip_info;
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if (!conf)
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return;
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/* Find CPU map of supported C-states */
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info = cpu_info();
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if (!info)
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return;
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cpu = find_cpu_driver(info->cpu);
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if (!cpu || !cpu->cstates)
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return;
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acpigen_emit_byte(0x14); /* MethodOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("_CST");
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acpigen_emit_byte(0x00); /* No Arguments */
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/* If running on AC power */
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acpigen_emit_byte(0xa0); /* IfOp */
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acpigen_write_len_f(); /* PkgLength */
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acpigen_emit_namestring("PWRS");
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acpigen_emit_byte(0xa4); /* ReturnOp */
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generate_cstate_entries(cpu->cstates, conf->c1_acpower,
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conf->c2_acpower, conf->c3_acpower);
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acpigen_pop_len();
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/* Else on battery power */
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acpigen_emit_byte(0xa4); /* ReturnOp */
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generate_cstate_entries(cpu->cstates, conf->c1_battery,
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conf->c2_battery, conf->c3_battery);
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acpigen_pop_len();
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}
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static int calculate_power(int tdp, int p1_ratio, int ratio)
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{
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u32 m;
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@ -307,19 +307,19 @@ void generate_cpu_entries(const struct device *device)
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/* Generate processor \_SB.CPUx */
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acpigen_write_processor(
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(cpuID-1)*cores_per_package+coreID-1,
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(cpuID - 1) * cores_per_package+coreID - 1,
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pcontrol_blk, plen);
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/* Generate P-state tables */
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generate_P_state_entries(
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coreID-1, cores_per_package);
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coreID - 1, cores_per_package);
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/* Generate C-state tables */
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generate_C_state_entries();
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/* Generate T-state tables */
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generate_T_state_entries(
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cpuID-1, cores_per_package);
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cpuID - 1, cores_per_package);
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acpigen_pop_len();
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}
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@ -156,7 +156,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
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{
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uintptr_t tseg_base;
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size_t tseg_size;
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u32 prmrr_base;
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u32 prmrr_size;
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int phys_bits;
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@ -197,7 +196,7 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
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params->uncore_prmrr_base.lo = prmrr_base;
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params->uncore_prmrr_base.hi = 0;
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params->uncore_prmrr_mask.lo = (~(prmrr_size - 1) & rmask) |
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MTRR_PHYS_MASK_VALID;
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MTRR_PHYS_MASK_VALID;
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params->uncore_prmrr_mask.hi = (1 << (39 - 32)) - 1;
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}
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@ -282,6 +281,5 @@ void smm_lock(void)
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* make the SMM registers writable again.
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*/
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printk(BIOS_DEBUG, "Locking SMM.\n");
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pci_write_config8(pcidev_on_root(0, 0), SMRAM,
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D_LCK | G_SMRAME | C_BASE_SEG);
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pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
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}
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@ -2,9 +2,10 @@
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/* Global Variables */
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Name(\PICM, 0) // IOAPIC/8259
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Name (\PICM, 0) // IOAPIC/8259
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/* Global ACPI memory region. This region is used for passing information
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/*
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* Global ACPI memory region. This region is used for passing information
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* between coreboot (aka "the system bios"), ACPI, and the SMI handler.
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* Since we don't know where this will end up in memory at ACPI compile time,
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* we have to fix it up in coreboot's ACPI creation phase.
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@ -31,9 +32,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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PWRS, 8, // 0x10 - Power State (AC = 1)
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/* Thermal policy */
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Offset (0x11),
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TLVL, 8, // 0x11 - Throttle Level Limit
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TLVL, 8, // 0x11 - Throttle Level Limit
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FLVL, 8, // 0x12 - Current FAN Level
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TCRT, 8, // 0x13 - Critical Threshold
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TCRT, 8, // 0x13 - Critical Threshold
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TPSV, 8, // 0x14 - Passive Threshold
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TMAX, 8, // 0x15 - CPU Tj_max
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F0OF, 8, // 0x16 - FAN 0 OFF Threshold
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@ -51,7 +52,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
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F4OF, 8, // 0x22 - FAN 4 OFF Threshold
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F4ON, 8, // 0x23 - FAN 4 ON Threshold
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F4PW, 8, // 0x24 - FAN 4 PWM value
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TMPS, 8, // 0x25 - Temperature Sensor ID
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TMPS, 8, // 0x25 - Temperature Sensor ID
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/* Processor Identification */
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Offset (0x28),
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APIC, 8, // 0x28 - APIC Enabled by coreboot
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@ -4,7 +4,7 @@
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Device (LPCB)
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{
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Name(_ADR, 0x001f0000)
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Name (_ADR, 0x001f0000)
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OperationRegion(LPC0, PCI_Config, 0x00, 0x100)
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Field (LPC0, AnyAcc, NoLock, Preserve)
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@ -14,7 +14,7 @@ Device (LPCB)
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Offset (0x40),
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PMBS, 16, // PMBASE
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Offset (0x48),
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GPBS, 16, // GPIOBASE
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GPBS, 16, // GPIOBASE
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Offset (0x60), // Interrupt Routing Registers
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PRTA, 8,
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PRTB, 8,
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@ -40,10 +40,10 @@ Device (LPCB)
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#include "acpi/ec.asl"
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Device (DMAC) // DMA Controller
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Device (DMAC) // DMA Controller
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{
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Name(_HID, EISAID("PNP0200"))
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Name(_CRS, ResourceTemplate()
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Name (_HID, EISAID("PNP0200"))
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x00, 0x00, 0x01, 0x20)
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IO (Decode16, 0x81, 0x81, 0x01, 0x11)
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@ -53,7 +53,7 @@ Device (LPCB)
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})
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}
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Device (FWH) // Firmware Hub
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Device (FWH) // Firmware Hub
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{
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Name (_HID, EISAID("INT0800"))
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Name (_CRS, ResourceTemplate()
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@ -67,7 +67,7 @@ Device (LPCB)
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Name (_HID, EISAID("PNP0103"))
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Name (_CID, 0x010CD041)
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Name(BUF0, ResourceTemplate()
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Name (BUF0, ResourceTemplate()
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{
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Memory32Fixed(ReadOnly, CONFIG_HPET_ADDRESS, 0x400, FED0)
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})
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@ -90,7 +90,7 @@ Device (LPCB)
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Method (_CRS, 0, Serialized) // Current resources
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{
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If (HPTE) {
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CreateDWordField(BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
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CreateDWordField (BUF0, \_SB.PCI0.LPCB.HPET.FED0._BAS, HPT0)
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If (Lequal(HPAS, 1)) {
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Add(CONFIG_HPET_ADDRESS, 0x1000, HPT0)
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}
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@ -110,8 +110,8 @@ Device (LPCB)
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Device(PIC) // 8259 Interrupt Controller
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{
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Name(_HID,EISAID("PNP0000"))
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Name(_CRS, ResourceTemplate()
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Name (_HID,EISAID("PNP0000"))
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Name (_CRS, ResourceTemplate()
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{
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IO (Decode16, 0x20, 0x20, 0x01, 0x02)
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IO (Decode16, 0x24, 0x24, 0x01, 0x02)
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@ -160,8 +160,7 @@ Device (LPCB)
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IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
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IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
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IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
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IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE,
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0x1, 0xff)
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IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff)
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// GPIO region may be 128 bytes or 4096 bytes
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IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1)
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@ -197,9 +196,8 @@ Device (LPCB)
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Device (TIMR) // Intel 8254 timer
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{
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Name(_HID, EISAID("PNP0100"))
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Name(_CRS, ResourceTemplate()
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{
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Name (_HID, EISAID("PNP0100"))
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Name (_CRS, ResourceTemplate() {
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IO (Decode16, 0x40, 0x40, 0x01, 0x04)
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IO (Decode16, 0x50, 0x50, 0x10, 0x04)
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IRQNoFlags() {0}
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@ -1,8 +1,8 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* Intel Cougar Point PCH support */
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/* Intel Lynx Point PCH support */
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Scope(\)
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Scope (\)
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{
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// Return TRUE if chipset is LynxPoint-LP
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Method (ISLP, 0, NotSerialized)
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@ -11,17 +11,16 @@ Scope(\)
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}
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// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
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OperationRegion(IO_T, SystemIO, 0x800, 0x10)
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Field(IO_T, ByteAcc, NoLock, Preserve)
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OperationRegion (IO_T, SystemIO, 0x800, 0x10)
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Field (IO_T, ByteAcc, NoLock, Preserve)
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{
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Offset(0x8),
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Offset (0x8),
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TRP0, 8 // IO-Trap at 0x808
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}
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// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
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OperationRegion(RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
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Field(RCRB, DWordAcc, Lock, Preserve)
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// Root Complex Register Block
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OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
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Field (RCRB, DWordAcc, Lock, Preserve)
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{
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Offset(0x3404), // High Performance Timer Configuration
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HPAS, 2, // Address Select
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@ -116,7 +116,7 @@ Device (SDMA)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
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})
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Method (_CRS, 0, NotSerialized)
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@ -156,7 +156,7 @@ Device (I2C0)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
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})
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// DMA channels are only used if Serial IO DMA controller is enabled
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@ -236,7 +236,7 @@ Device (I2C1)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
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})
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// DMA channels are only used if Serial IO DMA controller is enabled
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@ -313,7 +313,7 @@ Device (SPI0)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
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})
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Method (_CRS, 0, NotSerialized)
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@ -350,7 +350,7 @@ Device (SPI1)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {7}
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {7}
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})
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// DMA channels are only used if Serial IO DMA controller is enabled
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@ -399,7 +399,7 @@ Device (UAR0)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13}
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
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})
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// DMA channels are only used if Serial IO DMA controller is enabled
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@ -448,7 +448,7 @@ Device (UAR1)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {13}
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {13}
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})
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Method (_CRS, 0, NotSerialized)
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@ -485,7 +485,7 @@ Device (SDIO)
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Name (RBUF, ResourceTemplate ()
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{
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Memory32Fixed (ReadWrite, 0x00000000, 0x00000000, BAR0)
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , ,) {5}
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Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) {5}
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})
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Method (_CRS, 0, NotSerialized)
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|
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@ -47,7 +47,8 @@ struct southbridge_intel_lynxpoint_config {
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uint32_t sata_port0_gen3_dtle;
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uint32_t sata_port1_gen3_dtle;
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/* SATA DEVSLP Mux
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/*
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* SATA DEVSLP Mux
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* 0 = port 0 DEVSLP on DEVSLP0/GPIO33
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* 1 = port 3 DEVSLP on DEVSLP0/GPIO33
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*/
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@ -67,12 +68,13 @@ struct southbridge_intel_lynxpoint_config {
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/* Enable linear PCIe Root Port function numbers starting at zero */
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uint8_t pcie_port_coalesce;
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/* Force root port ASPM configuration with port bitmap */
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uint8_t pcie_port_force_aspm;
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/* Serial IO configuration */
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/* Put devices into ACPI mode instead of a PCI device */
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/* Put SerialIO devices into ACPI mode instead of a PCI device */
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uint8_t sio_acpi_mode;
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/* I2C voltage select: 0=3.3V 1=1.8V */
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uint8_t sio_i2c0_voltage;
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uint8_t sio_i2c1_voltage;
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@ -91,4 +93,4 @@ struct southbridge_intel_lynxpoint_config {
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bool docking_supported;
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};
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#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
|
||||
#endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_CHIP_H */
|
||||
|
|
|
@ -46,7 +46,7 @@ static void pch_log_gpe(void)
|
|||
u16 pmbase = get_pmbase();
|
||||
u32 gpe0_sts, gpe0_en;
|
||||
int gpe0_high_gpios[] = {
|
||||
[0] = 27,
|
||||
[0] = 27,
|
||||
[24] = 17,
|
||||
[25] = 19,
|
||||
[26] = 21,
|
||||
|
|
|
@ -115,7 +115,7 @@ static void pch_pirq_init(struct device *dev)
|
|||
*/
|
||||
|
||||
for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
|
||||
u8 int_pin=0, int_line=0;
|
||||
u8 int_pin = 0, int_line = 0;
|
||||
|
||||
if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI)
|
||||
continue;
|
||||
|
@ -446,7 +446,7 @@ static void enable_lp_clock_gating(struct device *dev)
|
|||
reg32 &= ~(1 << 29); // LPC Dynamic
|
||||
else
|
||||
reg32 |= (1 << 29); // LPC Dynamic
|
||||
reg32 |= (1UL << 31); // LP LPC
|
||||
reg32 |= (1 << 31); // LP LPC
|
||||
reg32 |= (1 << 30); // LP BLA
|
||||
reg32 |= (1 << 28); // GPIO Dynamic
|
||||
reg32 |= (1 << 27); // HPET Dynamic
|
||||
|
@ -565,7 +565,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
|
|||
res->base = (resource_t)(uintptr_t)DEFAULT_RCBA;
|
||||
res->size = 16 * 1024;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
|
||||
IORESOURCE_FIXED | IORESOURCE_RESERVE;
|
||||
IORESOURCE_FIXED | IORESOURCE_RESERVE;
|
||||
}
|
||||
|
||||
/* Check LPC Memory Decode register. */
|
||||
|
@ -577,7 +577,7 @@ static void pch_lpc_add_mmio_resources(struct device *dev)
|
|||
res->base = reg;
|
||||
res->size = 16 * 1024;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED |
|
||||
IORESOURCE_FIXED | IORESOURCE_RESERVE;
|
||||
IORESOURCE_FIXED | IORESOURCE_RESERVE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
@ -645,8 +645,7 @@ static void pch_lpc_add_io_resources(struct device *dev)
|
|||
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
/* GPIOBASE */
|
||||
pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE,
|
||||
GPIO_BASE);
|
||||
pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE);
|
||||
|
||||
/* PMBASE */
|
||||
pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE);
|
||||
|
|
|
@ -11,7 +11,7 @@ static const char *me_cws_values[] = {
|
|||
[ME_HFS_CWS_NORMAL] = "Normal",
|
||||
[ME_HFS_CWS_WAIT] = "Platform Disable Wait",
|
||||
[ME_HFS_CWS_TRANS] = "OP State Transition",
|
||||
[ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In"
|
||||
[ME_HFS_CWS_INVALID] = "Invalid CPU Plugged In",
|
||||
};
|
||||
|
||||
/* HFS1[8:6] Current Operation State Values */
|
||||
|
|
|
@ -502,14 +502,10 @@ static void pcie_add_0x0202000_iobp(u32 reg)
|
|||
|
||||
static void pch_pcie_early(struct device *dev)
|
||||
{
|
||||
int rp;
|
||||
int do_aspm;
|
||||
int is_lp;
|
||||
struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
|
||||
|
||||
rp = root_port_number(dev);
|
||||
do_aspm = 0;
|
||||
is_lp = pch_is_lp();
|
||||
int do_aspm = 0;
|
||||
int rp = root_port_number(dev);
|
||||
int is_lp = pch_is_lp();
|
||||
|
||||
if (is_lp) {
|
||||
switch (rp) {
|
||||
|
@ -517,18 +513,24 @@ static void pch_pcie_early(struct device *dev)
|
|||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
/* Bits 31:28 of b0d28f0 0x32c register correspnd to
|
||||
* Root Ports 4:1. */
|
||||
/*
|
||||
* Bits 31:28 of b0d28f0 0x32c register correspond to
|
||||
* Root Ports 4:1.
|
||||
*/
|
||||
do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
|
||||
break;
|
||||
case 5:
|
||||
/* Bit 28 of b0d28f4 0x32c register correspnd to
|
||||
* Root Ports 4:1. */
|
||||
/*
|
||||
* Bit 28 of b0d28f4 0x32c register correspond to
|
||||
* Root Ports 4:1.
|
||||
*/
|
||||
do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
|
||||
break;
|
||||
case 6:
|
||||
/* Bit 28 of b0d28f5 0x32c register correspnd to
|
||||
* Root Ports 4:1. */
|
||||
/*
|
||||
* Bit 28 of b0d28f5 0x32c register correspond to
|
||||
* Root Ports 4:1.
|
||||
*/
|
||||
do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
|
||||
break;
|
||||
}
|
||||
|
@ -538,16 +540,20 @@ static void pch_pcie_early(struct device *dev)
|
|||
case 2:
|
||||
case 3:
|
||||
case 4:
|
||||
/* Bits 31:28 of b0d28f0 0x32c register correspnd to
|
||||
* Root Ports 4:1. */
|
||||
/*
|
||||
* Bits 31:28 of b0d28f0 0x32c register correspond to
|
||||
* Root Ports 4:1.
|
||||
*/
|
||||
do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
|
||||
break;
|
||||
case 5:
|
||||
case 6:
|
||||
case 7:
|
||||
case 8:
|
||||
/* Bit 31:28 of b0d28f4 0x32c register correspnd to
|
||||
* Root Ports 8:5. */
|
||||
/*
|
||||
* Bits 31:28 of b0d28f4 0x32c register correspond to
|
||||
* Root Ports 8:5.
|
||||
*/
|
||||
do_aspm = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5)));
|
||||
break;
|
||||
}
|
||||
|
@ -644,7 +650,7 @@ static void pch_pcie_early(struct device *dev)
|
|||
pci_or_config32(dev, 0x64, 1 << 11);
|
||||
pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
|
||||
|
||||
pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16));
|
||||
pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
|
||||
|
||||
/* Set L1 exit latency in LCAP register. */
|
||||
if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
|
||||
|
@ -692,7 +698,7 @@ static void pch_pcie_early(struct device *dev)
|
|||
pci_update_config32(dev, 0x90, ~0, 0);
|
||||
}
|
||||
|
||||
static void pci_init(struct device *dev)
|
||||
static void pch_pcie_init(struct device *dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
|
||||
|
||||
|
@ -737,7 +743,7 @@ static struct device_operations device_ops = {
|
|||
.read_resources = pci_bus_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_bus_enable_resources,
|
||||
.init = pci_init,
|
||||
.init = pch_pcie_init,
|
||||
.enable = pch_pcie_enable,
|
||||
.scan_bus = pciexp_scan_bridge,
|
||||
.ops_pci = &pci_dev_ops_pci,
|
||||
|
|
|
@ -33,8 +33,8 @@ static void print_status_bits(u32 status, const char *bit_names[])
|
|||
if (!status)
|
||||
return;
|
||||
|
||||
for (i=31; i>=0; i--) {
|
||||
if (status & (1UL << i)) {
|
||||
for (i = 31; i >= 0; i--) {
|
||||
if (status & (1 << i)) {
|
||||
if (bit_names[i])
|
||||
printk(BIOS_DEBUG, "%s ", bit_names[i]);
|
||||
else
|
||||
|
@ -51,7 +51,7 @@ static void print_gpio_status(u32 status, int start)
|
|||
if (!status)
|
||||
return;
|
||||
|
||||
for (i=31; i>=0; i--) {
|
||||
for (i = 31; i >= 0; i--) {
|
||||
if (status & (1 << i))
|
||||
printk(BIOS_DEBUG, "GPIO%d ", start + i);
|
||||
}
|
||||
|
|
|
@ -86,7 +86,7 @@ static void southbridge_smi_sleep(void)
|
|||
u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
|
||||
u16 pmbase = get_pmbase();
|
||||
|
||||
// save and recover RTC port values
|
||||
/* save and recover RTC port values */
|
||||
u8 tmp70, tmp72;
|
||||
tmp70 = inb(0x70);
|
||||
tmp72 = inb(0x72);
|
||||
|
@ -145,11 +145,10 @@ static void southbridge_smi_sleep(void)
|
|||
* "KEEP", switch to "OFF" - KEEP is software emulated
|
||||
*/
|
||||
reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
|
||||
if (s5pwr == MAINBOARD_POWER_ON) {
|
||||
if (s5pwr == MAINBOARD_POWER_ON)
|
||||
reg8 &= ~1;
|
||||
} else {
|
||||
else
|
||||
reg8 |= 1;
|
||||
}
|
||||
pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
|
||||
|
||||
/* also iterates over all bridges on bus 0 */
|
||||
|
@ -160,7 +159,8 @@ static void southbridge_smi_sleep(void)
|
|||
break;
|
||||
}
|
||||
|
||||
/* Write back to the SLP register to cause the originally intended
|
||||
/*
|
||||
* Write back to the SLP register to cause the originally intended
|
||||
* event again. We need to set BIT13 (SLP_EN) though to make the
|
||||
* sleep happen.
|
||||
*/
|
||||
|
@ -170,7 +170,8 @@ static void southbridge_smi_sleep(void)
|
|||
if (slp_typ >= ACPI_S3)
|
||||
halt();
|
||||
|
||||
/* In most sleep states, the code flow of this function ends at
|
||||
/*
|
||||
* In most sleep states, the code flow of this function ends at
|
||||
* the line above. However, if we entered sleep state S1 and wake
|
||||
* up again, we will continue to execute code in this function.
|
||||
*/
|
||||
|
@ -228,11 +229,11 @@ static void southbridge_smi_gsmi(void)
|
|||
return;
|
||||
|
||||
/* Command and return value in EAX */
|
||||
ret = (u32*)&io_smi->rax;
|
||||
ret = (u32 *)&io_smi->rax;
|
||||
sub_command = (u8)(*ret >> 8);
|
||||
|
||||
/* Parameter buffer in EBX */
|
||||
param = (u32*)&io_smi->rbx;
|
||||
param = (u32 *)&io_smi->rbx;
|
||||
|
||||
/* drivers/elog/gsmi.c */
|
||||
*ret = gsmi_exec(sub_command, param);
|
||||
|
@ -345,7 +346,7 @@ static void southbridge_smi_pm1(void)
|
|||
* on a power button event.
|
||||
*/
|
||||
if (pm1_sts & PWRBTN_STS) {
|
||||
// power button pressed
|
||||
/* power button pressed */
|
||||
elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
|
||||
disable_pm1_control(-1UL);
|
||||
enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
|
||||
|
@ -367,9 +368,7 @@ static void southbridge_smi_gpi(void)
|
|||
|
||||
static void southbridge_smi_mc(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = inl(get_pmbase() + SMI_EN);
|
||||
u32 reg32 = inl(get_pmbase() + SMI_EN);
|
||||
|
||||
/* Are microcontroller SMIs enabled? */
|
||||
if ((reg32 & MCSMI_EN) == 0)
|
||||
|
@ -386,17 +385,16 @@ static void southbridge_smi_tco(void)
|
|||
if (!tco_sts)
|
||||
return;
|
||||
|
||||
if (tco_sts & (1 << 8)) { // BIOSWR
|
||||
u8 bios_cntl;
|
||||
|
||||
bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
|
||||
// BIOSWR
|
||||
if (tco_sts & (1 << 8)) {
|
||||
u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
|
||||
|
||||
if (bios_cntl & 1) {
|
||||
/* BWE is RW, so the SMI was caused by a
|
||||
/*
|
||||
* BWE is RW, so the SMI was caused by a
|
||||
* write to BWE, not by a write to the BIOS
|
||||
*/
|
||||
|
||||
/* This is the place where we notice someone
|
||||
*
|
||||
* This is the place where we notice someone
|
||||
* is trying to tinker with the BIOS. We are
|
||||
* trying to be nice and just ignore it. A more
|
||||
* resolute answer would be to power down the
|
||||
|
@ -413,9 +411,7 @@ static void southbridge_smi_tco(void)
|
|||
|
||||
static void southbridge_smi_periodic(void)
|
||||
{
|
||||
u32 reg32;
|
||||
|
||||
reg32 = inl(get_pmbase() + SMI_EN);
|
||||
u32 reg32 = inl(get_pmbase() + SMI_EN);
|
||||
|
||||
/* Are periodic SMIs enabled? */
|
||||
if ((reg32 & PERIODIC_EN) == 0)
|
||||
|
@ -435,7 +431,7 @@ static void southbridge_smi_monitor(void)
|
|||
RCBA32(0x1e00) = trap_sts; // Clear trap(s) in TRSR
|
||||
|
||||
trap_cycle = RCBA32(0x1e10);
|
||||
for (i=16; i<20; i++) {
|
||||
for (i = 16; i < 20; i++) {
|
||||
if (trap_cycle & (1 << i))
|
||||
mask |= (0xff << ((i - 16) << 2));
|
||||
}
|
||||
|
@ -452,7 +448,8 @@ static void southbridge_smi_monitor(void)
|
|||
|
||||
/* IOTRAP(0) SMIC */
|
||||
if (IOTRAP(0)) {
|
||||
if (!(trap_cycle & (1 << 24))) { // It's a write
|
||||
// It's a write
|
||||
if (!(trap_cycle & (1 << 24))) {
|
||||
printk(BIOS_DEBUG, "SMI1 command\n");
|
||||
(void)RCBA32(0x1e18);
|
||||
// data = RCBA32(0x1e18);
|
||||
|
@ -466,8 +463,9 @@ static void southbridge_smi_monitor(void)
|
|||
|
||||
printk(BIOS_DEBUG, " trapped io address = 0x%x\n",
|
||||
trap_cycle & 0xfffc);
|
||||
for (i=0; i < 4; i++)
|
||||
if (IOTRAP(i)) printk(BIOS_DEBUG, " TRAP = %d\n", i);
|
||||
for (i = 0; i < 4; i++)
|
||||
if (IOTRAP(i))
|
||||
printk(BIOS_DEBUG, " TRAP = %d\n", i);
|
||||
printk(BIOS_DEBUG, " AHBE = %x\n", (trap_cycle >> 16) & 0xf);
|
||||
printk(BIOS_DEBUG, " MASK = 0x%08x\n", mask);
|
||||
printk(BIOS_DEBUG, " read/write: %s\n",
|
||||
|
|
Loading…
Reference in New Issue