haswell/lynxpoint: Align cosmetics with Broadwell

Tested with BUILD_TIMELESS=1, Google Wolf does not change.

Change-Id: Ibd8430352e860ffc0e2030fd7bc73582982f4695
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45698
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/cpu/intel/haswell/acpi.c

@@ -65,50 +65,6 @@ static void generate_cstate_entries(acpi_cstate_t *cstates,
 	acpigen_pop_len();
 }
 
-static void generate_C_state_entries(void)
-{
-	struct cpu_info *info;
-	struct cpu_driver *cpu;
-	struct device *lapic;
-	struct cpu_intel_haswell_config *conf = NULL;
-
-	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
-	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
-	if (!lapic)
-		return;
-	conf = lapic->chip_info;
-	if (!conf)
-		return;
-
-	/* Find CPU map of supported C-states */
-	info = cpu_info();
-	if (!info)
-		return;
-	cpu = find_cpu_driver(info->cpu);
-	if (!cpu || !cpu->cstates)
-		return;
-
-	acpigen_emit_byte(0x14);		/* MethodOp */
-	acpigen_write_len_f();		/* PkgLength */
-	acpigen_emit_namestring("_CST");
-	acpigen_emit_byte(0x00);		/* No Arguments */
-
-	/* If running on AC power */
-	acpigen_emit_byte(0xa0);		/* IfOp */
-	acpigen_write_len_f();		/* PkgLength */
-	acpigen_emit_namestring("PWRS");
-	acpigen_emit_byte(0xa4);	/* ReturnOp */
-	generate_cstate_entries(cpu->cstates, conf->c1_acpower,
-					 conf->c2_acpower, conf->c3_acpower);
-	acpigen_pop_len();
-
-	/* Else on battery power */
-	acpigen_emit_byte(0xa4);	/* ReturnOp */
-	generate_cstate_entries(cpu->cstates, conf->c1_battery,
-					conf->c2_battery, conf->c3_battery);
-	acpigen_pop_len();
-}
-
 static acpi_tstate_t tss_table_fine[] = {
 	{ 100, 1000, 0, 0x00, 0 },
 	{ 94, 940, 0, 0x1f, 0 },
@@ -161,6 +117,50 @@ static void generate_T_state_entries(int core, int cores_per_package)
 			ARRAY_SIZE(tss_table_coarse), tss_table_coarse);
 }
 
+static void generate_C_state_entries(void)
+{
+	struct cpu_info *info;
+	struct cpu_driver *cpu;
+	struct device *lapic;
+	struct cpu_intel_haswell_config *conf = NULL;
+
+	/* Find the SpeedStep CPU in the device tree using magic APIC ID */
+	lapic = dev_find_lapic(SPEEDSTEP_APIC_MAGIC);
+	if (!lapic)
+		return;
+	conf = lapic->chip_info;
+	if (!conf)
+		return;
+
+	/* Find CPU map of supported C-states */
+	info = cpu_info();
+	if (!info)
+		return;
+	cpu = find_cpu_driver(info->cpu);
+	if (!cpu || !cpu->cstates)
+		return;
+
+	acpigen_emit_byte(0x14);		/* MethodOp */
+	acpigen_write_len_f();		/* PkgLength */
+	acpigen_emit_namestring("_CST");
+	acpigen_emit_byte(0x00);		/* No Arguments */
+
+	/* If running on AC power */
+	acpigen_emit_byte(0xa0);		/* IfOp */
+	acpigen_write_len_f();		/* PkgLength */
+	acpigen_emit_namestring("PWRS");
+	acpigen_emit_byte(0xa4);	/* ReturnOp */
+	generate_cstate_entries(cpu->cstates, conf->c1_acpower,
+					 conf->c2_acpower, conf->c3_acpower);
+	acpigen_pop_len();
+
+	/* Else on battery power */
+	acpigen_emit_byte(0xa4);	/* ReturnOp */
+	generate_cstate_entries(cpu->cstates, conf->c1_battery,
+					conf->c2_battery, conf->c3_battery);
+	acpigen_pop_len();
+}
+
 static int calculate_power(int tdp, int p1_ratio, int ratio)
 {
 	u32 m;

src/cpu/intel/haswell/smmrelocate.c

@@ -156,7 +156,6 @@ static void fill_in_relocation_params(struct smm_relocation_params *params)
 {
 	uintptr_t tseg_base;
 	size_t tseg_size;
-
 	u32 prmrr_base;
 	u32 prmrr_size;
 	int phys_bits;
@@ -282,6 +281,5 @@ void smm_lock(void)
 	 * make the SMM registers writable again.
 	 */
 	printk(BIOS_DEBUG, "Locking SMM.\n");
-	pci_write_config8(pcidev_on_root(0, 0), SMRAM,
+	pci_write_config8(pcidev_on_root(0, 0), SMRAM, D_LCK | G_SMRAME | C_BASE_SEG);
-			D_LCK | G_SMRAME | C_BASE_SEG);
 }

src/southbridge/intel/lynxpoint/acpi/globalnvs.asl

@@ -4,7 +4,8 @@
 
 Name (\PICM, 0)		// IOAPIC/8259
 
-/* Global ACPI memory region. This region is used for passing information
+/*
+ * Global ACPI memory region. This region is used for passing information
  * between coreboot (aka "the system bios"), ACPI, and the SMI handler.
  * Since we don't know where this will end up in memory at ACPI compile time,
  * we have to fix it up in coreboot's ACPI creation phase.

src/southbridge/intel/lynxpoint/acpi/lpc.asl

@@ -160,8 +160,7 @@ Device (LPCB)
 			IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post
 			IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved
 			IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
-			IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE,
+			IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0xff)
-			    0x1, 0xff)
 
 			// GPIO region may be 128 bytes or 4096 bytes
 			IO (Decode16, 0x0000, 0x0000, 0x1, 0x00, GPR1)
@@ -198,8 +197,7 @@ Device (LPCB)
 	Device (TIMR)	// Intel 8254 timer
 	{
 		Name (_HID, EISAID("PNP0100"))
-		Name(_CRS, ResourceTemplate()
+		Name (_CRS, ResourceTemplate() {
-		{
 			IO (Decode16, 0x40, 0x40, 0x01, 0x04)
 			IO (Decode16, 0x50, 0x50, 0x10, 0x04)
 			IRQNoFlags() {0}

src/southbridge/intel/lynxpoint/acpi/pch.asl

@@ -1,6 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-/* Intel Cougar Point PCH support */
+/* Intel Lynx Point PCH support */
 
 Scope (\)
 {
@@ -11,7 +11,6 @@ Scope(\)
 	}
 
 	// IO-Trap at 0x800. This is the ACPI->SMI communication interface.
-
 	OperationRegion (IO_T, SystemIO, 0x800, 0x10)
 	Field (IO_T, ByteAcc, NoLock, Preserve)
 	{
@@ -19,7 +18,7 @@ Scope(\)
 		TRP0, 8		// IO-Trap at 0x808
 	}
 
-	// ICH7 Root Complex Register Block. Memory Mapped through RCBA)
+	// Root Complex Register Block
 	OperationRegion (RCRB, SystemMemory, DEFAULT_RCBA, 0x4000)
 	Field (RCRB, DWordAcc, Lock, Preserve)
 	{

src/southbridge/intel/lynxpoint/chip.h

@@ -47,7 +47,8 @@ struct southbridge_intel_lynxpoint_config {
 	uint32_t sata_port0_gen3_dtle;
 	uint32_t sata_port1_gen3_dtle;
 
-	/* SATA DEVSLP Mux
+	/*
+	 * SATA DEVSLP Mux
 	 * 0 = port 0 DEVSLP on DEVSLP0/GPIO33
 	 * 1 = port 3 DEVSLP on DEVSLP0/GPIO33
 	 */
@@ -67,12 +68,13 @@ struct southbridge_intel_lynxpoint_config {
 
 	/* Enable linear PCIe Root Port function numbers starting at zero */
 	uint8_t pcie_port_coalesce;
+
 	/* Force root port ASPM configuration with port bitmap */
 	uint8_t pcie_port_force_aspm;
 
-	/* Serial IO configuration */
+	/* Put SerialIO devices into ACPI mode instead of a PCI device */
-	/* Put devices into ACPI mode instead of a PCI device */
 	uint8_t sio_acpi_mode;
+
 	/* I2C voltage select: 0=3.3V 1=1.8V */
 	uint8_t sio_i2c0_voltage;
 	uint8_t sio_i2c1_voltage;

src/southbridge/intel/lynxpoint/lpc.c

@@ -446,7 +446,7 @@ static void enable_lp_clock_gating(struct device *dev)
 		reg32 &= ~(1 << 29); // LPC Dynamic
 	else
 		reg32 |= (1 << 29); // LPC Dynamic
-	reg32 |= (1UL << 31); // LP LPC
+	reg32 |= (1 << 31); // LP LPC
 	reg32 |= (1 << 30); // LP BLA
 	reg32 |= (1 << 28); // GPIO Dynamic
 	reg32 |= (1 << 27); // HPET Dynamic
@@ -645,8 +645,7 @@ static void pch_lpc_add_io_resources(struct device *dev)
 	res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
 
 	/* GPIOBASE */
-	pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE,
+	pch_lpc_add_io_resource(dev, get_gpiobase(), DEFAULT_GPIOSIZE, GPIO_BASE);
-	                        GPIO_BASE);
 
 	/* PMBASE */
 	pch_lpc_add_io_resource(dev, get_pmbase(), 256, PMBASE);

src/southbridge/intel/lynxpoint/me_status.c

@@ -11,7 +11,7 @@ static const char *me_cws_values[] = {
 	[ME_HFS_CWS_NORMAL]	= "Normal",
 	[ME_HFS_CWS_WAIT]	= "Platform Disable Wait",
 	[ME_HFS_CWS_TRANS]	= "OP State Transition",
-	[ME_HFS_CWS_INVALID]	= "Invalid CPU Plugged In"
+	[ME_HFS_CWS_INVALID]	= "Invalid CPU Plugged In",
 };
 
 /* HFS1[8:6] Current Operation State Values */

src/southbridge/intel/lynxpoint/pcie.c

@@ -502,14 +502,10 @@ static void pcie_add_0x0202000_iobp(u32 reg)
 
 static void pch_pcie_early(struct device *dev)
 {
-	int rp;
-	int do_aspm;
-	int is_lp;
 	struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
-
+	int do_aspm = 0;
-	rp = root_port_number(dev);
+	int rp = root_port_number(dev);
-	do_aspm = 0;
+	int is_lp = pch_is_lp();
-	is_lp = pch_is_lp();
 
 	if (is_lp) {
 		switch (rp) {
@@ -517,18 +513,24 @@ static void pch_pcie_early(struct device *dev)
 		case 2:
 		case 3:
 		case 4:
-			/* Bits 31:28 of b0d28f0 0x32c register correspnd to
+			/*
-			 * Root Ports 4:1. */
+			 * Bits 31:28 of b0d28f0 0x32c register correspond to
+			 * Root Ports 4:1.
+			 */
 			do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
 			break;
 		case 5:
-			/* Bit 28 of b0d28f4 0x32c register correspnd to
+			/*
-			 * Root Ports 4:1. */
+			 * Bit 28 of b0d28f4 0x32c register correspond to
+			 * Root Ports 4:1.
+			 */
 			do_aspm = !!(rpc.b0d28f4_32c & (1 << 28));
 			break;
 		case 6:
-			/* Bit 28 of b0d28f5 0x32c register correspnd to
+			/*
-			 * Root Ports 4:1. */
+			 * Bit 28 of b0d28f5 0x32c register correspond to
+			 * Root Ports 4:1.
+			 */
 			do_aspm = !!(rpc.b0d28f5_32c & (1 << 28));
 			break;
 		}
@@ -538,16 +540,20 @@ static void pch_pcie_early(struct device *dev)
 		case 2:
 		case 3:
 		case 4:
-			/* Bits 31:28 of b0d28f0 0x32c register correspnd to
+			/*
-			 * Root Ports 4:1. */
+			 * Bits 31:28 of b0d28f0 0x32c register correspond to
+			 * Root Ports 4:1.
+			 */
 			do_aspm = !!(rpc.b0d28f0_32c & (1 << (28 + rp - 1)));
 			break;
 		case 5:
 		case 6:
 		case 7:
 		case 8:
-			/* Bit 31:28 of b0d28f4 0x32c register correspnd to
+			/*
-			 * Root Ports 8:5. */
+			 * Bits 31:28 of b0d28f4 0x32c register correspond to
+			 * Root Ports 8:5.
+			 */
 			do_aspm = !!(rpc.b0d28f4_32c & (1 << (28 + rp - 5)));
 			break;
 		}
@@ -644,7 +650,7 @@ static void pch_pcie_early(struct device *dev)
 	pci_or_config32(dev, 0x64, 1 << 11);
 	pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10));
 
-	pci_update_config32(dev, 0x318, ~(0xffffUL << 16), (0x1414UL << 16));
+	pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16));
 
 	/* Set L1 exit latency in LCAP register. */
 	if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1))
@@ -692,7 +698,7 @@ static void pch_pcie_early(struct device *dev)
 	pci_update_config32(dev, 0x90, ~0, 0);
 }
 
-static void pci_init(struct device *dev)
+static void pch_pcie_init(struct device *dev)
 {
 	printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
 
@@ -737,7 +743,7 @@ static struct device_operations device_ops = {
 	.read_resources		= pci_bus_read_resources,
 	.set_resources		= pci_dev_set_resources,
 	.enable_resources	= pci_bus_enable_resources,
-	.init			= pci_init,
+	.init			= pch_pcie_init,
 	.enable			= pch_pcie_enable,
 	.scan_bus		= pciexp_scan_bridge,
 	.ops_pci		= &pci_dev_ops_pci,

src/southbridge/intel/lynxpoint/pmutil.c

@@ -34,7 +34,7 @@ static void print_status_bits(u32 status, const char *bit_names[])
 		return;
 
 	for (i = 31; i >= 0; i--) {
-		if (status & (1UL << i)) {
+		if (status & (1 << i)) {
 			if (bit_names[i])
 				printk(BIOS_DEBUG, "%s ", bit_names[i]);
 			else

src/southbridge/intel/lynxpoint/smihandler.c

@@ -86,7 +86,7 @@ static void southbridge_smi_sleep(void)
 	u8 s5pwr = CONFIG_MAINBOARD_POWER_FAILURE_STATE;
 	u16 pmbase = get_pmbase();
 
-	// save and recover RTC port values
+	/* save and recover RTC port values */
 	u8 tmp70, tmp72;
 	tmp70 = inb(0x70);
 	tmp72 = inb(0x72);
@@ -145,11 +145,10 @@ static void southbridge_smi_sleep(void)
 		 * "KEEP", switch to "OFF" - KEEP is software emulated
 		 */
 		reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
-		if (s5pwr == MAINBOARD_POWER_ON) {
+		if (s5pwr == MAINBOARD_POWER_ON)
 			reg8 &= ~1;
-		} else {
+		else
 			reg8 |= 1;
-		}
 		pci_write_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3, reg8);
 
 		/* also iterates over all bridges on bus 0 */
@@ -160,7 +159,8 @@ static void southbridge_smi_sleep(void)
 		break;
 	}
 
-	/* Write back to the SLP register to cause the originally intended
+	/*
+	 * Write back to the SLP register to cause the originally intended
 	 * event again. We need to set BIT13 (SLP_EN) though to make the
 	 * sleep happen.
 	 */
@@ -170,7 +170,8 @@ static void southbridge_smi_sleep(void)
 	if (slp_typ >= ACPI_S3)
 		halt();
 
-	/* In most sleep states, the code flow of this function ends at
+	/*
+	 * In most sleep states, the code flow of this function ends at
 	 * the line above. However, if we entered sleep state S1 and wake
 	 * up again, we will continue to execute code in this function.
 	 */
@@ -345,7 +346,7 @@ static void southbridge_smi_pm1(void)
 	 * on a power button event.
 	 */
 	if (pm1_sts & PWRBTN_STS) {
-		// power button pressed
+		/* power button pressed */
 		elog_gsmi_add_event(ELOG_TYPE_POWER_BUTTON);
 		disable_pm1_control(-1UL);
 		enable_pm1_control(SLP_EN | (SLP_TYP_S5 << 10));
@@ -367,9 +368,7 @@ static void southbridge_smi_gpi(void)
 
 static void southbridge_smi_mc(void)
 {
-	u32 reg32;
+	u32 reg32 = inl(get_pmbase() + SMI_EN);
-
-	reg32 = inl(get_pmbase() + SMI_EN);
 
 	/* Are microcontroller SMIs enabled? */
 	if ((reg32 & MCSMI_EN) == 0)
@@ -386,17 +385,16 @@ static void southbridge_smi_tco(void)
 	if (!tco_sts)
 		return;
 
-	if (tco_sts & (1 << 8)) { // BIOSWR
+	// BIOSWR
-		u8 bios_cntl;
+	if (tco_sts & (1 << 8)) {
-
+		u8 bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
-		bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc);
 
 		if (bios_cntl & 1) {
-			/* BWE is RW, so the SMI was caused by a
+			/*
+			 * BWE is RW, so the SMI was caused by a
 			 * write to BWE, not by a write to the BIOS
-			 */
+			 *
-
+			 * This is the place where we notice someone
-			/* This is the place where we notice someone
 			 * is trying to tinker with the BIOS. We are
 			 * trying to be nice and just ignore it. A more
 			 * resolute answer would be to power down the
@@ -413,9 +411,7 @@ static void southbridge_smi_tco(void)
 
 static void southbridge_smi_periodic(void)
 {
-	u32 reg32;
+	u32 reg32 = inl(get_pmbase() + SMI_EN);
-
-	reg32 = inl(get_pmbase() + SMI_EN);
 
 	/* Are periodic SMIs enabled? */
 	if ((reg32 & PERIODIC_EN) == 0)
@@ -452,7 +448,8 @@ static void southbridge_smi_monitor(void)
 
 	/* IOTRAP(0) SMIC */
 	if (IOTRAP(0)) {
-		if (!(trap_cycle & (1 << 24))) { // It's a write
+		// It's a write
+		if (!(trap_cycle & (1 << 24))) {
 			printk(BIOS_DEBUG, "SMI1 command\n");
 			(void)RCBA32(0x1e18);
 			// data = RCBA32(0x1e18);
@@ -467,7 +464,8 @@ static void southbridge_smi_monitor(void)
 	printk(BIOS_DEBUG, "  trapped io address = 0x%x\n",
 	       trap_cycle & 0xfffc);
 	for (i = 0; i < 4; i++)
-		if (IOTRAP(i)) printk(BIOS_DEBUG, "  TRAP = %d\n", i);
+		if (IOTRAP(i))
+			printk(BIOS_DEBUG, "  TRAP = %d\n", i);
 	printk(BIOS_DEBUG, "  AHBE = %x\n", (trap_cycle >> 16) & 0xf);
 	printk(BIOS_DEBUG, "  MASK = 0x%08x\n", mask);
 	printk(BIOS_DEBUG, "  read/write: %s\n",