diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 528fd4a0bf..31f809a475 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -288,4 +288,28 @@ config INTEL_TXT_BIOSACM_ALIGNMENT
 	hex
 	default 0x40000 # 256KB
 
+config MAINBOARD_SUPPORTS_SKYLAKE_CPU
+	bool "Board can contain Skylake CPU"
+	default y
+
+if SKYLAKE_SOC_PCH_H
+
+config MAINBOARD_SUPPORTS_KABYLAKE_CPU
+	bool "Board can contain Kaby Lake CPU"
+	default y if SOC_INTEL_KABYLAKE
+
+endif
+
+if !SKYLAKE_SOC_PCH_H
+
+config MAINBOARD_SUPPORTS_KABYLAKE_DUAL
+	bool "Board can contain Kaby Lake DUAL core"
+	default y
+
+config MAINBOARD_SUPPORTS_KABYLAKE_QUAD
+	bool "Board can contain Kaby Lake QUAD core"
+	default y
+
+endif
+
 endif
diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc
index c0937385f0..75121abe0d 100644
--- a/src/soc/intel/skylake/Makefile.inc
+++ b/src/soc/intel/skylake/Makefile.inc
@@ -79,18 +79,28 @@ postcar-y += i2c.c
 postcar-y += uart.c
 
 ifeq ($(CONFIG_SKYLAKE_SOC_PCH_H),y)
+ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y)
 # Skylake H Q0
 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-5e-03
+endif
+ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_CPU),y)
 # Kabylake H B0 S0
 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-9e-09
+endif
 else
+ifeq ($(CONFIG_MAINBOARD_SUPPORTS_SKYLAKE_CPU),y)
 # Skylake D0
 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-4e-03
+endif
+ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_DUAL),y)
 # Kabylake H0, J0, J1
 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-09
+endif
+ifeq ($(CONFIG_MAINBOARD_SUPPORTS_KABYLAKE_QUAD),y)
 # Kabylake Y0
 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-8e-0a
 endif
+endif
 # Missing for Skylake C0 (0x406e2), Kabylake G0 (0x406e8), Kabylake HA0 (0x506e8)
 # since those are probably pre-release samples.