Major merge of YhLu's code from 2004/04/20: add s2875, various other updates,
cleanups. Drop "driver" code from mainboard directories and use them from the driver directory instead git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
parent
f05dcb8d7a
commit
2ab88d1179
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@ -1,6 +1,9 @@
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uses HAVE_MP_TABLE
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uses HAVE_PIRQ_TABLE
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uses USE_FALLBACK_IMAGE
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uses LB_CKS_RANGE_START
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uses LB_CKS_RANGE_END
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uses LB_CKS_LOC
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uses MAINBOARD
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uses ARCH
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uses HARD_RESET_BUS
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@ -22,13 +25,19 @@ register "fixup_scsi" = "1"
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register "fixup_vga" = "1"
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##
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## Move the default LinuxBIOS cmos range off of AMD RTC registers
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##
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default LB_CKS_RANGE_START=49
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default LB_CKS_RANGE_END=122
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default LB_CKS_LOC=123
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driver mainboard.o
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driver adaptec_scsi.o
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driver promise_sata.o
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driver intel_nic.o
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driver broadcom_nic.o
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#driver adaptec_scsi.o
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#driver si_sata.o
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#driver intel_nic_ipmi.o
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#driver broadcom_nic_ipmi.o
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#object reset.o
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#object static_devices.o
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if HAVE_MP_TABLE object mptable.o end
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#
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@ -44,6 +53,7 @@ arch i386 end
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###
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mainboardinit cpu/i386/entry16.inc
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mainboardinit cpu/i386/entry32.inc
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mainboardinit cpu/i386/bist32.inc
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ldscript /cpu/i386/entry16.lds
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ldscript /cpu/i386/entry32.lds
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#
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@ -95,9 +105,9 @@ end
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###
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### Setup the serial port
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###
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#mainboardinit superiowinbond/w83627hf/setup_serial.inc
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mainboardinit pc80/serial.inc
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mainboardinit arch/i386/lib/console.inc
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mainboardinit cpu/i386/bist32_fail.inc
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#
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####
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#### O.k. We aren't just an intermediary anymore!
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@ -114,9 +124,6 @@ mainboardinit arch/i386/lib/console.inc
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###
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### Romcc output
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###
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#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
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#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
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#mainboardinit .failover.inc
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makerule ./failover.E
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depends "$(MAINBOARD)/failover.c"
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@ -125,16 +132,16 @@ end
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makerule ./failover.inc
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depends "./romcc ./failover.E"
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
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action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
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end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c"
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action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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depends "$(MAINBOARD)/auto.c option_table.h"
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action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
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end
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makerule ./auto.inc
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depends "./romcc ./auto.E"
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action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
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action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
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end
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mainboardinit cpu/k8/enable_mmx_sse.inc
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mainboardinit ./auto.inc
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@ -143,6 +150,7 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
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###
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### Include the secondary Configuration files
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###
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northbridge amd/amdk8 "mc0"
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pci 0:18.0
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pci 0:18.0
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@ -162,22 +170,38 @@ northbridge amd/amdk8 "mc0"
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pci 1:0.1 on
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pci 1:0.2 on
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pci 1:1.0 off
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superio winbond/w83627hf link 1
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pnp 2e.0 on # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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pnp 2e.1 off # Parallel Port
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io 0x60 = 0x378
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irq 0x70 = 7
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pnp 2e.2 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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pnp 2e.3 off # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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pnp 2e.5 on # Keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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irq 0x72 = 12
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pnp 2e.6 off # CIR
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pnp 2e.7 off # GAME_MIDI_GIPO1
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pnp 2e.8 off # GPIO2
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pnp 2e.9 off # GPIO3
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pnp 2e.a off # ACPI
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pnp 2e.b on # HW Monitor
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io 0x60 = 0x290
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end
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end
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end
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#northbridge amd/amdk8
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#end
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#southbridge amd/amd8111 "amd8111"
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#end
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#mainboardinit archi386/smp/secondary.inc
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#superio NSC/pc87360
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# register "com1" = "{1}"
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# register "lpt" = "{1}"
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#end
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dir /pc80
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##dir /src/superio/winbond/w83627hf
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#dir /bioscall
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#dir /cpu/k8
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cpu k8 "cpu0"
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register "up" = "{.chip = &amd8111, .ht_width=8, .ht_speed=200}"
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end
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@ -1,13 +1,16 @@
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#define ASSEMBLY 1
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#include <stdint.h>
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#include <device/pci_def.h>
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#include <cpu/p6/apic.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/smp/lapic.h>
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#include "option_table.h"
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#include "pc80/mc146818rtc_early.c"
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#include "pc80/serial.c"
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#include "arch/i386/lib/console.c"
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#include "ram/ramtest.c"
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#include "northbridge/amd/amdk8/early_ht.c"
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#include "northbridge/amd/amdk8/incoherent_ht.c"
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#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
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#include "northbridge/amd/amdk8/raminit.h"
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#include "cpu/k8/apic_timer.c"
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@ -16,89 +19,99 @@
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#include "northbridge/amd/amdk8/reset_test.c"
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#include "northbridge/amd/amdk8/debug.c"
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#include "northbridge/amd/amdk8/cpu_rev.c"
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#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
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#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
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static void hard_reset(void)
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{
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set_bios_reset();
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/* enable cf9 */
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pci_write_config8(PCI_DEV(0, 0x02, 3), 0x41, 0xf1);
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/* reset */
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outb(0x0e, 0x0cf9);
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}
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static void soft_reset(void)
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{
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set_bios_reset();
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pci_write_config8(PCI_DEV(0, 0x02, 0), 0x47, 1);
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}
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#define REV_B_RESET 0
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static void memreset_setup(void)
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{
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#if REV_B_RESET==1
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if (is_cpu_pre_c0()) {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
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#else
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}
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else {
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
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#endif
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}
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outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
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}
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static void memreset(int controllers, const struct mem_controller *ctrl)
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{
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if (is_cpu_pre_c0()) {
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udelay(800);
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#if REV_B_RESET==1
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outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
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#endif
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udelay(90);
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}
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}
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static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
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{
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/* Routing Table Node i
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*
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* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
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* i: 0, 1, 2, 3, 4, 5, 6, 7
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*
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* [ 0: 3] Request Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [11: 8] Response Route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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* [19:16] Broadcast route
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* [0] Route to this node
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* [1] Route to Link 0
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* [2] Route to Link 1
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* [3] Route to Link 2
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*/
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uint32_t ret=0x00010101; /* default row entry */
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return ret;
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}
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static inline void activate_spd_rom(const struct mem_controller *ctrl)
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{
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/* nothing to do */
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}
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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/* include mainboard specific ht code */
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#include "hypertransport.c"
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//#include "northbridge/amd/amdk8/cpu_ldtstop.c"
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//#include "southbridge/amd/amd8111/amd8111_ldtstop.c"
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#include "northbridge/amd/amdk8/raminit.c"
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#include "northbridge/amd/amdk8/coherent_ht.c"
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#include "sdram/generic_sdram.c"
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static void enable_lapic(void)
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{
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msr_t msr;
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msr = rdmsr(0x1b);
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msr.hi &= 0xffffff00;
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msr.lo &= 0x000007ff;
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msr.lo |= APIC_DEFAULT_BASE | (1 << 11);
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wrmsr(0x1b, msr);
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}
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static void stop_this_cpu(void)
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{
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unsigned apicid;
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apicid = apic_read(APIC_ID) >> 24;
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/* Send an APIC INIT to myself */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* Deassert the APIC INIT */
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apic_write(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
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apic_write(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
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/* Wait for the ipi send to finish */
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apic_wait_icr_idle();
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/* If I haven't halted spin forever */
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for(;;) {
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hlt();
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}
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}
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#define FIRST_CPU 1
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#define SECOND_CPU 0
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#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
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static void main(void)
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{
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/*
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* GPIO28 of 8111 will control H0_MEMRESET_L
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* GPIO29 of 8111 will control H1_MEMRESET_L
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*/
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static const struct mem_controller cpu[] = {
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#if FIRST_CPU
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{
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.node_id = 0,
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.f0 = PCI_DEV(0, 0x18, 0),
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@ -108,42 +121,37 @@ static void main(void)
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.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
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.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
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},
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#endif
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#if SECOND_CPU
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{
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.node_id = 1,
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.f0 = PCI_DEV(0, 0x19, 0),
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.f1 = PCI_DEV(0, 0x19, 1),
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.f2 = PCI_DEV(0, 0x19, 2),
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.f3 = PCI_DEV(0, 0x19, 3),
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.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
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.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
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},
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#endif
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};
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int needs_reset;
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enable_lapic();
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init_timer();
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if (cpu_init_detected()) {
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asm("jmp __cpu_reset");
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}
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enable_lapic();
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init_timer();
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if (!boot_cpu() ) {
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notify_bsp_ap_is_stopped();
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distinguish_cpu_resets();
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if (!boot_cpu()) {
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stop_this_cpu();
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}
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w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
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uart_init();
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console_init();
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setup_default_resource_map();
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setup_coherent_ht_domain();
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enumerate_ht_chain(0);
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distinguish_cpu_resets(0);
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needs_reset = setup_coherent_ht_domain();
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needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
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if (needs_reset) {
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print_info("ht reset -\r\n");
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soft_reset();
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}
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#if 0
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print_pci_devices();
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#endif
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enable_smbus();
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#if 0
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dump_spd_registers(&cpu[0]);
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// dump_spd_registers(&cpu[0]);
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dump_smbus_registers();
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#endif
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memreset_setup();
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sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
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|
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@ -29,6 +29,9 @@ entries
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386 1 e 1 ECC_memory
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388 4 r 0 reboot_bits
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392 3 e 5 baud_rate
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395 1 e 1 hw_scrubber
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396 1 e 1 interleave_chip_selects
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397 2 e 8 max_mem_clock
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400 1 e 1 power_on_after_fail
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412 4 e 6 debug_level
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416 4 e 7 boot_first
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@ -36,7 +39,14 @@ entries
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424 4 e 7 boot_third
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428 4 h 0 boot_index
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432 8 h 0 boot_countdown
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1008 16 h 0 check_sum
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440 4 e 9 slow_cpu
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444 1 e 1 nmi
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728 256 h 0 user_data
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984 16 h 0 check_sum
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# Reserve the extended AMD configuration registers
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1000 24 r 0 reserved_memory
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enumerations
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@ -66,9 +76,21 @@ enumerations
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7 9 Fallback_HDD
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7 10 Fallback_Floppy
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#7 3 ROM
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8 0 200Mhz
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8 1 166Mhz
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8 2 133Mhz
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||||
8 3 100Mhz
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||||
9 0 off
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9 1 87.5%
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9 2 75.0%
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9 3 62.5%
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9 4 50.0%
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9 5 37.5%
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9 6 25.0%
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9 7 12.5%
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checksums
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|
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checksum 392 1007 1008
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checksum 392 983 984
|
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|
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|
|
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@ -3,36 +3,78 @@
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#include <device/pci_def.h>
|
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#include <device/pci_ids.h>
|
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#include <arch/io.h>
|
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#include "arch/romcc_io.h"
|
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#include <arch/romcc_io.h>
|
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#include <arch/smp/lapic.h>
|
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#include "pc80/mc146818rtc_early.c"
|
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#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
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#include "northbridge/amd/amdk8/early_ht.c"
|
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#include "cpu/p6/boot_cpu.c"
|
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#include "northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
#define HAVE_REGPARM_SUPPORT 0
|
||||
#if HAVE_REGPARM_SUPPORT
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
#else
|
||||
static void main(void)
|
||||
{
|
||||
unsigned long bist = 0;
|
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#endif
|
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/* Make cerain my local apic is useable */
|
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enable_lapic();
|
||||
|
||||
/* Is this a cpu only reset? */
|
||||
if (cpu_init_detected()) {
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto cpu_reset;
|
||||
}
|
||||
}
|
||||
/* Is this a secondary cpu? */
|
||||
if (!boot_cpu()) {
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
enumerate_ht_chain(0);
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Setup the 8111 */
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Is this a cpu reset? */
|
||||
if (cpu_init_detected()) {
|
||||
if (last_boot_normal()) {
|
||||
asm("jmp __normal_image");
|
||||
} else {
|
||||
asm("jmp __cpu_reset");
|
||||
}
|
||||
}
|
||||
/* Is this a secondary cpu? */
|
||||
else if (!boot_cpu() && last_boot_normal()) {
|
||||
asm("jmp __normal_image");
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal()) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
asm("jmp __normal_image");
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
#if HAVE_REGPARM_SUPPORT
|
||||
return bist;
|
||||
#else
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
|
|
|||
|
|
@ -22,15 +22,15 @@ const struct irq_routing_table intel_irq_routing_table = {
|
|||
{
|
||||
{1,(2<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x2,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x2,0x68, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x58, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x18, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x2,0x30, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
|
||||
{0x2,0x38, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
|
||||
{0x2,0x40, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x2,0x48, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0},
|
||||
{0x2,0x50, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x5, 0},
|
||||
{0x2,0x70, {{0x1, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0x60, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,(0x0d<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,(0x0b<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x2,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x1, 0},
|
||||
{0x2,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x2, 0},
|
||||
{0x2,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x2,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x4, 0},
|
||||
{0x2,(0x0a<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x6, 0},
|
||||
{0x2,(0x0e<<3)|0, {{0x1, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,(0x0c<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ static void fixup_lsi_53c1030(struct device *pdev)
|
|||
}
|
||||
#endif
|
||||
//extern static void lsi_scsi_init(struct device *dev);
|
||||
#if 1
|
||||
#if 0
|
||||
static void print_pci_regs(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
|
|
@ -120,7 +120,7 @@ static void onboard_scsi_fixup(void)
|
|||
// print_mem();
|
||||
// amd8111_enable_rom();
|
||||
}
|
||||
#if 1
|
||||
#if 0
|
||||
static void vga_fixup(void) {
|
||||
// we do this right here because:
|
||||
// - all the hardware is working, and some VGA bioses seem to need
|
||||
|
|
@ -154,8 +154,8 @@ enable(struct chip *chip, enum chip_pass pass)
|
|||
case CONF_PASS_PRE_BOOT:
|
||||
if (conf->fixup_scsi)
|
||||
onboard_scsi_fixup();
|
||||
if (conf->fixup_vga)
|
||||
vga_fixup();
|
||||
// if (conf->fixup_vga)
|
||||
// vga_fixup();
|
||||
printk_debug("mainboard fixup pass %d done\r\n",
|
||||
pass);
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -11,6 +11,10 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
static const char productid[12] = "S2850 ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_8111_1;
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
|
|
@ -29,43 +33,107 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc, processor_map);
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||
|
||||
bus_8111_1 = 2;
|
||||
bus_isa = 3;
|
||||
}
|
||||
}
|
||||
/*Bus: Bus ID Type*/
|
||||
smp_write_bus(mc, 0, "PCI ");
|
||||
smp_write_bus(mc, 1, "PCI ");
|
||||
smp_write_bus(mc, 2, "PCI ");
|
||||
smp_write_bus(mc, 3, "ISA ");
|
||||
/* define bus and isa numbers */
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 1, 0x11, 0xfec00000);
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x1, 0x1, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x0, 0x1, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x3, 0x1, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x4, 0x1, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x5, 0x1, 0x5);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x6, 0x1, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x7, 0x1, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0x8, 0x1, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xc, 0x1, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xd, 0x1, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xe, 0x1, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x3, 0xf, 0x1, 0xf);
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x1, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x1, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x1, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x1, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x1, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x1, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x1, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x1, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x1, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x1, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x1, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x1, 0xf);
|
||||
|
||||
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (2<<2)|3, 0x1, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x3, 0x1, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x34, 0x1, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x2c, 0x1, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x2, 0x38, 0x1, 0x10);
|
||||
|
||||
//On Board AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x1, 0x13);
|
||||
|
||||
//On Board ATI Display Adapter
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x1, 0x12);
|
||||
|
||||
//Onboard Broadcom 5705 NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0d<<2)|0, 0x1, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0e<<2)|0, 0x1, 0x10);
|
||||
//Onboard SI Serial ATA
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x1, 0x11);
|
||||
|
||||
|
||||
//PCI Slot 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|0, 0x1, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|1, 0x1, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|2, 0x1, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|3, 0x1, 0x13);
|
||||
|
||||
|
||||
//PCI Slot 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|0, 0x1, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|1, 0x1, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|2, 0x1, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|3, 0x1, 0x10);
|
||||
|
||||
|
||||
//PCI Slot 3
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|0, 0x1, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|1, 0x1, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|2, 0x1, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|3, 0x1, 0x11);
|
||||
|
||||
|
||||
//PCI Slot 4
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|0, 0x1, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|1, 0x1, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|2, 0x1, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|3, 0x1, 0x12);
|
||||
|
||||
//PCI Slot 5
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|0, 0x1, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|1, 0x1, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|2, 0x1, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|3, 0x1, 0x13);
|
||||
|
||||
//PCI Slot 6
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x1, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x1, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x1, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x1, 0x10);
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0x0, 0x0, MP_APIC_ALL, 0x1);
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
|
|
|
|||
|
|
@ -0,0 +1,220 @@
|
|||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses LB_CKS_RANGE_START
|
||||
uses LB_CKS_RANGE_END
|
||||
uses LB_CKS_LOC
|
||||
uses MAINBOARD
|
||||
uses ARCH
|
||||
uses HARD_RESET_BUS
|
||||
uses HARD_RESET_DEVICE
|
||||
uses HARD_RESET_FUNCTION
|
||||
|
||||
#
|
||||
#
|
||||
###
|
||||
### Set all of the defaults for an x86 architecture
|
||||
###
|
||||
|
||||
#
|
||||
#
|
||||
###
|
||||
### Build the objects we have code for in this directory.
|
||||
###
|
||||
|
||||
config chip.h
|
||||
register "fixup_scsi" = "1"
|
||||
register "fixup_vga" = "1"
|
||||
|
||||
|
||||
##
|
||||
## Move the default LinuxBIOS cmos range off of AMD RTC registers
|
||||
##
|
||||
default LB_CKS_RANGE_START=49
|
||||
default LB_CKS_RANGE_END=122
|
||||
default LB_CKS_LOC=123
|
||||
|
||||
driver mainboard.o
|
||||
#driver si_sata.o
|
||||
#driver intel_nic.o
|
||||
#object reset.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
#
|
||||
default HARD_RESET_BUS=1
|
||||
default HARD_RESET_DEVICE=5
|
||||
default HARD_RESET_FUNCTION=0
|
||||
#
|
||||
#
|
||||
arch i386 end
|
||||
|
||||
#
|
||||
###
|
||||
### Build our 16 bit and 32 bit linuxBIOS entry code
|
||||
###
|
||||
mainboardinit cpu/i386/entry16.inc
|
||||
mainboardinit cpu/i386/entry32.inc
|
||||
mainboardinit cpu/i386/bist32.inc
|
||||
ldscript /cpu/i386/entry16.lds
|
||||
ldscript /cpu/i386/entry32.lds
|
||||
|
||||
#
|
||||
###
|
||||
### Build our reset vector (This is where linuxBIOS is entered)
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/i386/reset16.inc
|
||||
ldscript /cpu/i386/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/i386/reset32.inc
|
||||
ldscript /cpu/i386/reset32.lds
|
||||
end
|
||||
#
|
||||
#### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
#
|
||||
###
|
||||
### Include an id string (For safe flashing)
|
||||
###
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
#
|
||||
####
|
||||
#### This is the early phase of linuxBIOS startup
|
||||
#### Things are delicate and we test to see if we should
|
||||
#### failover to another image.
|
||||
####
|
||||
#option MAX_REBOOT_CNT=2
|
||||
if USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
end
|
||||
#
|
||||
###
|
||||
### Setup our mtrrs
|
||||
###
|
||||
mainboardinit cpu/k8/earlymtrr.inc
|
||||
###
|
||||
### Only the bootstrap cpu makes it here.
|
||||
### Failover if we need to
|
||||
###
|
||||
#
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
#
|
||||
#
|
||||
###
|
||||
### Setup the serial port
|
||||
###
|
||||
mainboardinit pc80/serial.inc
|
||||
mainboardinit arch/i386/lib/console.inc
|
||||
mainboardinit cpu/i386/bist32_fail.inc
|
||||
#
|
||||
####
|
||||
#### O.k. We aren't just an intermediary anymore!
|
||||
####
|
||||
###
|
||||
### Romcc output
|
||||
###
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c"
|
||||
action "$(CPP) -I$(TOP)/src $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failover.E"
|
||||
end
|
||||
|
||||
makerule ./failover.inc
|
||||
depends "./romcc ./failover.E"
|
||||
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"
|
||||
end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h"
|
||||
action "$(CPP) -I$(TOP)/src -I. $(ROMCCPPFLAGS) $(CPPFLAGS) $(MAINBOARD)/auto.c > ./auto.E"
|
||||
end
|
||||
|
||||
makerule ./auto.inc
|
||||
depends "./romcc ./auto.E"
|
||||
action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
|
||||
end
|
||||
|
||||
mainboardinit cpu/k8/enable_mmx_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
mainboardinit cpu/k8/disable_mmx_sse.inc
|
||||
|
||||
#
|
||||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
dir /pc80
|
||||
|
||||
northbridge amd/amdk8 "mc0"
|
||||
pci 0:18.0
|
||||
pci 0:18.0
|
||||
pci 0:18.0
|
||||
pci 0:18.1
|
||||
pci 0:18.2
|
||||
pci 0:18.3
|
||||
southbridge amd/amd8151 "amd8151" link 0
|
||||
pci 0:0.0
|
||||
pci 0:1.0
|
||||
end
|
||||
southbridge amd/amd8111 "amd8111" link 0
|
||||
pci 0:0.0
|
||||
pci 0:1.0 on
|
||||
pci 0:1.1 on
|
||||
pci 0:1.2 on
|
||||
pci 0:1.3 on
|
||||
pci 0:1.5 on
|
||||
pci 0:1.6 off
|
||||
pci 1:0.0 on
|
||||
pci 1:0.1 on
|
||||
pci 1:0.2 on
|
||||
pci 1:1.0 off
|
||||
superio winbond/w83627hf link 1
|
||||
pnp 2e.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
irq 0x72 = 12
|
||||
pnp 2e.6 off # CIR
|
||||
pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
pnp 2e.8 off # GPIO2
|
||||
pnp 2e.9 off # GPIO3
|
||||
pnp 2e.a off # ACPI
|
||||
pnp 2e.b on # HW Monitor
|
||||
io 0x60 = 0x290
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
northbridge amd/amdk8 "mc1"
|
||||
pci 0:19.0
|
||||
pci 0:19.0
|
||||
pci 0:19.0
|
||||
pci 0:19.1
|
||||
pci 0:19.2
|
||||
pci 0:19.3
|
||||
end
|
||||
|
||||
#dir /bioscall
|
||||
|
||||
cpu k8 "cpu0"
|
||||
register "up" = "{.chip = &amd8151, .ht_width=16, .ht_speed=600}"
|
||||
end
|
||||
|
||||
cpu k8 "cpu1"
|
||||
end
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
2.0
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
#define ASSEMBLY 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <arch/smp/lapic.h>
|
||||
#include "option_table.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
#include "northbridge/amd/amdk8/incoherent_ht.c"
|
||||
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
|
||||
#include "northbridge/amd/amdk8/raminit.h"
|
||||
#include "cpu/k8/apic_timer.c"
|
||||
#include "lib/delay.c"
|
||||
#include "cpu/p6/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
#include "northbridge/amd/amdk8/debug.c"
|
||||
#include "northbridge/amd/amdk8/cpu_rev.c"
|
||||
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
|
||||
|
||||
static void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
|
||||
/* enable cf9 */
|
||||
pci_write_config8(PCI_DEV(0, 0x05, 3), 0x41, 0xf1);
|
||||
/* reset */
|
||||
outb(0x0e, 0x0cf9);
|
||||
}
|
||||
|
||||
static void soft_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
pci_write_config8(PCI_DEV(0, 0x05, 0), 0x47, 1);
|
||||
}
|
||||
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||
{
|
||||
/* Routing Table Node i
|
||||
*
|
||||
* F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
|
||||
* i: 0, 1, 2, 3, 4, 5, 6, 7
|
||||
*
|
||||
* [ 0: 3] Request Route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
* [11: 8] Response Route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
* [19:16] Broadcast route
|
||||
* [0] Route to this node
|
||||
* [1] Route to Link 0
|
||||
* [2] Route to Link 1
|
||||
* [3] Route to Link 2
|
||||
*/
|
||||
|
||||
uint32_t ret=0x00010101; /* default row entry */
|
||||
|
||||
static const unsigned int rows_2p[2][2] = {
|
||||
{ 0x00050101, 0x00010404 },
|
||||
{ 0x00010404, 0x00050101 }
|
||||
};
|
||||
|
||||
if(maxnodes>2) {
|
||||
print_debug("this mainboard is only designed for 2 cpus\r\n");
|
||||
maxnodes=2;
|
||||
}
|
||||
|
||||
|
||||
if (!(node>=maxnodes || row>=maxnodes)) {
|
||||
ret=rows_2p[node][row];
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static inline void activate_spd_rom(const struct mem_controller *ctrl)
|
||||
{
|
||||
/* nothing to do */
|
||||
}
|
||||
|
||||
static inline int spd_read_byte(unsigned device, unsigned address)
|
||||
{
|
||||
return smbus_read_byte(device, address);
|
||||
}
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
#include "sdram/generic_sdram.c"
|
||||
|
||||
#define FIRST_CPU 1
|
||||
#define SECOND_CPU 1
|
||||
#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
|
||||
static void main(void)
|
||||
{
|
||||
static const struct mem_controller cpu[] = {
|
||||
#if FIRST_CPU
|
||||
{
|
||||
.node_id = 0,
|
||||
.f0 = PCI_DEV(0, 0x18, 0),
|
||||
.f1 = PCI_DEV(0, 0x18, 1),
|
||||
.f2 = PCI_DEV(0, 0x18, 2),
|
||||
.f3 = PCI_DEV(0, 0x18, 3),
|
||||
.channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
#if SECOND_CPU
|
||||
{
|
||||
.node_id = 1,
|
||||
.f0 = PCI_DEV(0, 0x19, 0),
|
||||
.f1 = PCI_DEV(0, 0x19, 1),
|
||||
.f2 = PCI_DEV(0, 0x19, 2),
|
||||
.f3 = PCI_DEV(0, 0x19, 3),
|
||||
.channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
|
||||
.channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
int needs_reset;
|
||||
enable_lapic();
|
||||
init_timer();
|
||||
if (cpu_init_detected()) {
|
||||
asm("jmp __cpu_reset");
|
||||
}
|
||||
distinguish_cpu_resets();
|
||||
if (!boot_cpu()) {
|
||||
stop_this_cpu();
|
||||
}
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
setup_default_resource_map();
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
print_pci_devices();
|
||||
#endif
|
||||
enable_smbus();
|
||||
#if 0
|
||||
dump_spd_registers(&cpu[0]);
|
||||
#endif
|
||||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 1));
|
||||
#endif
|
||||
|
||||
/* Check all of memory */
|
||||
#if 0
|
||||
msr_t msr;
|
||||
msr = rdmsr(TOP_MEM2);
|
||||
print_debug("TOP_MEM2: ");
|
||||
print_debug_hex32(msr.hi);
|
||||
print_debug_hex32(msr.lo);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
/*
|
||||
#if 0
|
||||
ram_check(0x00000000, msr.lo+(msr.hi<<32));
|
||||
#else
|
||||
#if TOTAL_CPUS < 2
|
||||
// Check 16MB of memory @ 0
|
||||
ram_check(0x00000000, 0x00100000);
|
||||
#else
|
||||
// Check 16MB of memory @ 2GB
|
||||
ram_check(0x80000000, 0x80100000);
|
||||
#endif
|
||||
#endif
|
||||
*/
|
||||
}
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
extern struct chip_control mainboard_tyan_s2875_control;
|
||||
|
||||
struct mainboard_tyan_s2875_config {
|
||||
int fixup_scsi;
|
||||
int fixup_vga;
|
||||
};
|
||||
|
|
@ -0,0 +1,96 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
395 1 e 1 hw_scrubber
|
||||
396 1 e 1 interleave_chip_selects
|
||||
397 2 e 8 max_mem_clock
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
440 4 e 9 slow_cpu
|
||||
444 1 e 1 nmi
|
||||
728 256 h 0 user_data
|
||||
984 16 h 0 check_sum
|
||||
# Reserve the extended AMD configuration registers
|
||||
1000 24 r 0 reserved_memory
|
||||
|
||||
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
8 0 200Mhz
|
||||
8 1 166Mhz
|
||||
8 2 133Mhz
|
||||
8 3 100Mhz
|
||||
9 0 off
|
||||
9 1 87.5%
|
||||
9 2 75.0%
|
||||
9 3 62.5%
|
||||
9 4 50.0%
|
||||
9 5 37.5%
|
||||
9 6 25.0%
|
||||
9 7 12.5%
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 983 984
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,80 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <arch/smp/lapic.h>
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
|
||||
#include "northbridge/amd/amdk8/early_ht.c"
|
||||
#include "cpu/p6/boot_cpu.c"
|
||||
#include "northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
#define HAVE_REGPARM_SUPPORT 0
|
||||
#if HAVE_REGPARM_SUPPORT
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
#else
|
||||
static void main(void)
|
||||
{
|
||||
unsigned long bist = 0;
|
||||
#endif
|
||||
/* Make cerain my local apic is useable */
|
||||
enable_lapic();
|
||||
|
||||
/* Is this a cpu only reset? */
|
||||
if (cpu_init_detected()) {
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto cpu_reset;
|
||||
}
|
||||
}
|
||||
/* Is this a secondary cpu? */
|
||||
if (!boot_cpu()) {
|
||||
if (last_boot_normal()) {
|
||||
goto normal_image;
|
||||
} else {
|
||||
goto fallback_image;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/* Nothing special needs to be done to find bus 0 */
|
||||
/* Allow the HT devices to be found */
|
||||
enumerate_ht_chain();
|
||||
|
||||
/* Setup the 8111 */
|
||||
amd8111_enable_rom();
|
||||
|
||||
/* Is this a deliberate reset by the bios */
|
||||
if (bios_reset_detected() && last_boot_normal()) {
|
||||
goto normal_image;
|
||||
}
|
||||
/* This is the primary cpu how should I boot? */
|
||||
else if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
#if HAVE_REGPARM_SUPPORT
|
||||
return bist;
|
||||
#else
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,37 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
|
||||
|
||||
Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*13, /* there can be total 13 devices on the bus */
|
||||
1, /* Where the interrupt router lies (bus) */
|
||||
(5<<3)|3, /* Where the interrupt router lies (dev) */
|
||||
0, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1022, /* Vendor */
|
||||
0x746b, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xcf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{1,(5<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x3,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{1,(1<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x2,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x3,(7<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x4, 0},
|
||||
{0x3,(6<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x1, 0},
|
||||
{0x3,(8<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x3,(9<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x3, 0},
|
||||
{0x3,(5<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,(3<<3)|0, {{0x3, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,(0x0a<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x3,(0x0b<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0, 0}}, 0, 0},
|
||||
}
|
||||
};
|
||||
|
|
@ -0,0 +1,197 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/chip.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "../../../northbridge/amd/amdk8/northbridge.h"
|
||||
#include "chip.h"
|
||||
//#include <part/mainboard.h>
|
||||
unsigned long initial_apicid[CONFIG_MAX_CPUS] =
|
||||
{
|
||||
0,1
|
||||
};
|
||||
#if 0
|
||||
static void fixup_lsi_53c1030(struct device *pdev)
|
||||
{
|
||||
// uint8_t byte;
|
||||
uint16_t word;
|
||||
|
||||
byte = 1;
|
||||
pci_write_config8(pdev, 0xff, byte);
|
||||
// Set the device id
|
||||
// pci_write_config_word(pdev, PCI_DEVICE_ID, PCI_DEVICE_ID_LSILOGIC_53C1030);
|
||||
// Set the subsytem vendor id
|
||||
// pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, PCI_VENDOR_ID_TYAN);
|
||||
word = 0x10f1;
|
||||
pci_write_config16(pdev, PCI_SUBSYSTEM_VENDOR_ID, word);
|
||||
// Set the subsytem id
|
||||
word = 0x2880;
|
||||
pci_write_config16(pdev, PCI_SUBSYSTEM_ID, word);
|
||||
// Disable writes to the device id
|
||||
byte = 0;
|
||||
pci_write_config8(pdev, 0xff, byte);
|
||||
|
||||
// lsi_scsi_init(pdev);
|
||||
|
||||
}
|
||||
#endif
|
||||
//extern static void lsi_scsi_init(struct device *dev);
|
||||
#if 0
|
||||
static void print_pci_regs(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
int i;
|
||||
|
||||
for(i=0;i<256;i++) {
|
||||
byte = pci_read_config8(dev, i);
|
||||
|
||||
if((i%16)==0) printk_debug("\n%02x:",i);
|
||||
printk_debug(" %02x",byte);
|
||||
}
|
||||
printk_debug("\n");
|
||||
|
||||
// pci_write_config8(dev, 0x4, byte);
|
||||
|
||||
}
|
||||
#endif
|
||||
#if 0
|
||||
static void print_mem(void)
|
||||
{
|
||||
int i;
|
||||
int low_1MB = 0;
|
||||
for(i=low_1MB;i<low_1MB+1024*4;i++) {
|
||||
if((i%16)==0) printk_debug("\n %08x:",i);
|
||||
printk_debug(" %02x ",(unsigned char)*((unsigned char *)i));
|
||||
}
|
||||
|
||||
for(i=low_1MB;i<low_1MB+1024*4;i++) {
|
||||
if((i%16)==0) printk_debug("\n %08x:",i);
|
||||
printk_debug(" %c ",(unsigned char)*((unsigned char *)i));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
#if 0
|
||||
static void amd8111_enable_rom(void)
|
||||
{
|
||||
uint8_t byte;
|
||||
struct device *dev;
|
||||
|
||||
/* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */
|
||||
/* Locate the amd8111 */
|
||||
dev = dev_find_device(0x1022, 0x7468, 0);
|
||||
|
||||
/* Set the 4MB enable bit bit */
|
||||
byte = pci_read_config8(dev, 0x43);
|
||||
byte |= 0x80;
|
||||
pci_write_config8(dev, 0x43, byte);
|
||||
}
|
||||
#endif
|
||||
#if 0
|
||||
static void onboard_scsi_fixup(void)
|
||||
{
|
||||
struct device *dev;
|
||||
#if 1
|
||||
unsigned char i,j,k;
|
||||
|
||||
for(i=0;i<=6;i++) {
|
||||
for(j=0;j<=0x1f;j++) {
|
||||
for (k=0;k<=6;k++){
|
||||
dev = dev_find_slot(i, PCI_DEVFN(j, k));
|
||||
if (dev) {
|
||||
printk_debug("%02x:%02x:%02x",i,j,k);
|
||||
print_pci_regs(dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
#if 0
|
||||
dev = dev_find_device(PCI_VENDOR_ID_LSI_LOGIC, PCI_DEVICE_ID_LSI_53C1030,0);
|
||||
if(!dev) {
|
||||
printk_info("LSI_SCSI_FW_FIXUP: No Device Found!");
|
||||
return;
|
||||
}
|
||||
|
||||
lsi_scsi_init(dev);
|
||||
#endif
|
||||
// print_mem();
|
||||
// amd8111_enable_rom();
|
||||
}
|
||||
#endif
|
||||
#if 0
|
||||
static void vga_fixup(void) {
|
||||
// we do this right here because:
|
||||
// - all the hardware is working, and some VGA bioses seem to need
|
||||
// that
|
||||
// - we need page 0 below for linuxbios tables.
|
||||
#if CONFIG_REALMODE_IDT == 1
|
||||
printk_debug("INSTALL REAL-MODE IDT\n");
|
||||
setup_realmode_idt();
|
||||
#endif
|
||||
#if CONFIG_VGABIOS == 1
|
||||
printk_debug("DO THE VGA BIOS\n");
|
||||
do_vgabios(0x0600);
|
||||
post_code(0x93);
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
static void
|
||||
enable(struct chip *chip, enum chip_pass pass)
|
||||
{
|
||||
|
||||
struct mainboard_tyan_s2875_config *conf =
|
||||
(struct mainboard_tyan_s2875_config *)chip->chip_info;
|
||||
|
||||
switch (pass) {
|
||||
default: break;
|
||||
// case CONF_PASS_PRE_CONSOLE:
|
||||
// case CONF_PASS_PRE_PCI:
|
||||
// case CONF_PASS_POST_PCI:
|
||||
case CONF_PASS_PRE_BOOT:
|
||||
// if (conf->fixup_scsi)
|
||||
// onboard_scsi_fixup();
|
||||
// if (conf->fixup_vga)
|
||||
// vga_fixup();
|
||||
printk_debug("mainboard fixup pass %d done\r\n",
|
||||
pass);
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
void final_mainboard_fixup(void)
|
||||
{
|
||||
#if 0
|
||||
enable_ide_devices();
|
||||
#endif
|
||||
}
|
||||
static struct device_operations mainboard_operations = {
|
||||
.read_resources = root_dev_read_resources,
|
||||
.set_resources = root_dev_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = amdk8_scan_root_bus,
|
||||
.enable = 0,
|
||||
};
|
||||
|
||||
static void enumerate(struct chip *chip)
|
||||
{
|
||||
struct chip *child;
|
||||
dev_root.ops = &mainboard_operations;
|
||||
chip->dev = &dev_root;
|
||||
chip->bus = 0;
|
||||
for(child = chip->children; child; child = child->next) {
|
||||
child->bus = &dev_root.link[0];
|
||||
}
|
||||
}
|
||||
struct chip_control mainboard_tyan_s2875_control = {
|
||||
.enable = enable,
|
||||
.enumerate = enumerate,
|
||||
.name = "Tyan s2875 mainboard ",
|
||||
};
|
||||
|
|
@ -0,0 +1,172 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/smp/mpspec.h>
|
||||
#include <device/pci.h>
|
||||
#include <string.h>
|
||||
#include <stdint.h>
|
||||
|
||||
void *smp_write_config_table(void *v, unsigned long * processor_map)
|
||||
{
|
||||
static const char sig[4] = "PCMP";
|
||||
static const char oem[8] = "TYAN ";
|
||||
static const char productid[12] = "S2875 ";
|
||||
struct mp_config_table *mc;
|
||||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_8111_1;
|
||||
unsigned char bus_8151_1;
|
||||
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
memcpy(mc->mpc_signature, sig, sizeof(sig));
|
||||
mc->mpc_length = sizeof(*mc); /* initially just the header */
|
||||
mc->mpc_spec = 0x04;
|
||||
mc->mpc_checksum = 0; /* not yet computed */
|
||||
memcpy(mc->mpc_oem, oem, sizeof(oem));
|
||||
memcpy(mc->mpc_productid, productid, sizeof(productid));
|
||||
mc->mpc_oemptr = 0;
|
||||
mc->mpc_oemsize = 0;
|
||||
mc->mpc_entry_count = 0; /* No entries yet... */
|
||||
mc->mpc_lapic = LAPIC_ADDR;
|
||||
mc->mpe_length = 0;
|
||||
mc->mpe_checksum = 0;
|
||||
mc->reserved = 0;
|
||||
|
||||
smp_write_processors(mc, processor_map);
|
||||
|
||||
{
|
||||
device_t dev;
|
||||
|
||||
/* 8111 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x04,0));
|
||||
if (dev) {
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
printk_debug("bus_isa=%d\n",bus_isa);
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
|
||||
|
||||
bus_8111_1 = 3;
|
||||
bus_isa = 4;
|
||||
}
|
||||
/* 8151 */
|
||||
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
printk_debug("bus_8151_1=%d\n",bus_8151_1);
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
|
||||
bus_8151_1 = 2;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x4, 0x2, 0x4);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x6, 0x2, 0x6);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x7, 0x2, 0x7);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x8, 0x2, 0x8);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xc, 0x2, 0xc);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
|
||||
|
||||
|
||||
//??? What
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (5<<2)|3, 0x2, 0x13);
|
||||
//Onboard AMD AC97 Audio ???
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x1, (5<<2)|1, 0x2, 0x11);
|
||||
// Onboard AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
|
||||
|
||||
// AGP Display Adapter
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, 0x2, 0x10);
|
||||
|
||||
// Onboard Serial ATA
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x05<<2)|0, 0x2, 0x13);
|
||||
//Onboard Firewire
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x11);
|
||||
//Onboard Broadcom NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x03<<2)|0, 0x2, 0x12);
|
||||
|
||||
//Onboard VIA USB 1.1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|1, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|2, 0x2, 0x13);
|
||||
|
||||
//Slot 1
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|0, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|1, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|2, 0x2, 0x10); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x06<<2)|3, 0x2, 0x11); //
|
||||
|
||||
//Slot 2
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|0, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|1, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|2, 0x2, 0x13); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x08<<2)|3, 0x2, 0x10); //
|
||||
|
||||
//Slot 3
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|1, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|2, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x09<<2)|3, 0x2, 0x13); //
|
||||
|
||||
//Slot 4
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|0, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|1, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|2, 0x2, 0x11); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x07<<2)|3, 0x2, 0x12); //
|
||||
|
||||
|
||||
//Slot 5
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|1, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|2, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x04<<2)|3, 0x2, 0x13); //
|
||||
|
||||
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
|
||||
mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
|
||||
printk_debug("Wrote the mp table end at: %p - %p\n",
|
||||
mc, smp_next_mpe_entry(mc));
|
||||
return smp_next_mpe_entry(mc);
|
||||
}
|
||||
|
||||
unsigned long write_smp_table(unsigned long addr, unsigned long *processor_map)
|
||||
{
|
||||
void *v;
|
||||
v = smp_write_floating_table(addr);
|
||||
return (unsigned long)smp_write_config_table(v, processor_map);
|
||||
}
|
||||
|
|
@ -32,7 +32,7 @@ default LB_CKS_LOC=123
|
|||
|
||||
|
||||
driver mainboard.o
|
||||
driver lsi_scsi.o
|
||||
dir ../common/lsi_scsi
|
||||
#driver adaptec_scsi.o
|
||||
#driver promise_sata.o
|
||||
#driver intel_nic.o
|
||||
|
|
@ -126,8 +126,7 @@ makerule ./auto.E
|
|||
end
|
||||
makerule ./auto.inc
|
||||
depends "./romcc ./auto.E"
|
||||
action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
|
||||
# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
|
||||
action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
|
||||
end
|
||||
mainboardinit cpu/k8/enable_mmx_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
|
|
|||
|
|
@ -39,24 +39,24 @@ static void soft_reset(void)
|
|||
set_bios_reset();
|
||||
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
|
||||
}
|
||||
#define REV_B_RESET 0
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
#if REV_B_RESET==1
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
#else
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
#endif
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
#if REV_B_RESET==1
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
#endif
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||
|
|
@ -114,7 +114,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
|
|||
}
|
||||
|
||||
/* include mainboard specific ht code */
|
||||
#include "hypertransport.c"
|
||||
//#include "hypertransport.c"
|
||||
|
||||
#include "northbridge/amd/amdk8/raminit.c"
|
||||
#include "northbridge/amd/amdk8/coherent_ht.c"
|
||||
|
|
@ -166,7 +166,7 @@ static void main(void)
|
|||
needs_reset = setup_coherent_ht_domain();
|
||||
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\t");
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -37,7 +37,8 @@ driver mainboard.o
|
|||
#driver adaptec_scsi.o
|
||||
#driver si_sata.o
|
||||
#driver intel_nic.o
|
||||
#driver broadcom_nic.o
|
||||
#dir ../drivers/broadcom_nic_ipmi
|
||||
dir ../drivers/ati_graph
|
||||
#object reset.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
if HAVE_PIRQ_TABLE object irq_tables.o end
|
||||
|
|
@ -117,9 +118,6 @@ mainboardinit cpu/i386/bist32_fail.inc
|
|||
###
|
||||
### Romcc output
|
||||
###
|
||||
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
|
||||
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
|
||||
#mainboardinit .failover.inc
|
||||
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c"
|
||||
|
|
@ -128,7 +126,7 @@ end
|
|||
|
||||
makerule ./failover.inc
|
||||
depends "./romcc ./failover.E"
|
||||
action "./romcc -O -o failover.inc --label-prefix=failover ./failover.E"end
|
||||
action "./romcc -O2 -o failover.inc --label-prefix=failover ./failover.E"end
|
||||
|
||||
makerule ./auto.E
|
||||
depends "$(MAINBOARD)/auto.c option_table.h"
|
||||
|
|
@ -136,8 +134,7 @@ makerule ./auto.E
|
|||
end
|
||||
makerule ./auto.inc
|
||||
depends "./romcc ./auto.E"
|
||||
action "./romcc -O -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
|
||||
# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
|
||||
action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
|
||||
end
|
||||
mainboardinit cpu/k8/enable_mmx_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
|
@ -146,6 +143,9 @@ mainboardinit cpu/k8/disable_mmx_sse.inc
|
|||
###
|
||||
### Include the secondary Configuration files
|
||||
###
|
||||
|
||||
dir /pc80
|
||||
|
||||
northbridge amd/amdk8 "mc0"
|
||||
pci 0:18.0
|
||||
pci 0:18.0
|
||||
|
|
@ -171,31 +171,33 @@ northbridge amd/amdk8 "mc0"
|
|||
pci 1:0.1 on
|
||||
pci 1:0.2 on
|
||||
pci 1:1.0 off
|
||||
superio winbond/w83627hf link 1
|
||||
pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
pnp 2e.1 off # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
pnp 2e.2 on # Com1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
pnp 2e.3 off # Com2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
pnp 2e.6 off # CIR
|
||||
pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
pnp 2e.8 off # GPIO2
|
||||
pnp 2e.9 off # GPIO3
|
||||
pnp 2e.a off # ACPI
|
||||
pnp 2e.b off # HW Monitor
|
||||
end
|
||||
# superio winbond/w83627hf link 1
|
||||
# pnp 2e.0 on # Floppy
|
||||
# io 0x60 = 0x3f0
|
||||
# irq 0x70 = 6
|
||||
# drq 0x74 = 2
|
||||
# pnp 2e.1 off # Parallel Port
|
||||
# io 0x60 = 0x378
|
||||
# irq 0x70 = 7
|
||||
# pnp 2e.2 on # Com1
|
||||
# io 0x60 = 0x3f8
|
||||
# irq 0x70 = 4
|
||||
# pnp 2e.3 off # Com2
|
||||
# io 0x60 = 0x2f8
|
||||
# irq 0x70 = 3
|
||||
# pnp 2e.5 on # Keyboard
|
||||
# io 0x60 = 0x60
|
||||
# io 0x62 = 0x64
|
||||
# irq 0x70 = 1
|
||||
# irq 0x72 = 12
|
||||
# pnp 2e.6 off # CIR
|
||||
# pnp 2e.7 off # GAME_MIDI_GIPO1
|
||||
# pnp 2e.8 off # GPIO2
|
||||
# pnp 2e.9 off # GPIO3
|
||||
# pnp 2e.a off # ACPI
|
||||
# pnp 2e.b on # HW Monitor
|
||||
# io 0x60 = 0x290
|
||||
# end
|
||||
end
|
||||
end
|
||||
|
||||
|
|
@ -209,7 +211,6 @@ northbridge amd/amdk8 "mc1"
|
|||
end
|
||||
|
||||
|
||||
dir /pc80
|
||||
#dir /bioscall
|
||||
cpu k8 "cpu0"
|
||||
register "up" = "{.chip = &amd8131, .ht_width=16, .ht_speed=600}"
|
||||
|
|
|
|||
|
|
@ -39,24 +39,24 @@ static void soft_reset(void)
|
|||
pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
|
||||
}
|
||||
|
||||
#define REV_B_RESET 0
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
#if REV_B_RESET==1
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
#else
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
#endif
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
#if REV_B_RESET==1
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
#endif
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||
|
|
@ -165,7 +165,7 @@ static void main(void)
|
|||
needs_reset = setup_coherent_ht_domain();
|
||||
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\t");
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -18,7 +18,7 @@ const struct irq_routing_table intel_irq_routing_table = {
|
|||
0x746b, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x3d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
0x66, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{1,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x4,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
|
|
|
|||
|
|
@ -38,7 +38,7 @@ static void fixup_lsi_53c1030(struct device *pdev)
|
|||
}
|
||||
#endif
|
||||
//extern static void lsi_scsi_init(struct device *dev);
|
||||
#if 1
|
||||
#if 0
|
||||
static void print_pci_regs(struct device *dev)
|
||||
{
|
||||
uint8_t byte;
|
||||
|
|
@ -152,12 +152,11 @@ enable(struct chip *chip, enum chip_pass pass)
|
|||
// case CONF_PASS_PRE_PCI:
|
||||
// case CONF_PASS_POST_PCI:
|
||||
case CONF_PASS_PRE_BOOT:
|
||||
if (conf->fixup_scsi)
|
||||
onboard_scsi_fixup();
|
||||
// if (conf->fixup_scsi)
|
||||
// onboard_scsi_fixup();
|
||||
// if (conf->fixup_vga)
|
||||
// vga_fixup();
|
||||
printk_debug("mainboard fixup pass %d done\r\n",
|
||||
pass);
|
||||
// printk_debug("mainboard fixup pass %d done\r\n",pass);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, 0x3, 0x2);//
|
||||
|
||||
|
||||
//On Board NIC and LSI scsi
|
||||
//On Board NIC and adaptec scsi
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|1, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0xa<<2)|0, 0x3, 0x0);
|
||||
|
|
|
|||
|
|
@ -42,21 +42,22 @@ static void soft_reset(void)
|
|||
#define REV_B_RESET 0
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
#if REV_B_RESET==1
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
#else
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
#endif
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
#if REV_B_RESET==1
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
#endif
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -151,12 +151,11 @@ enable(struct chip *chip, enum chip_pass pass)
|
|||
// case CONF_PASS_PRE_PCI:
|
||||
case CONF_PASS_POST_PCI:
|
||||
case CONF_PASS_PRE_BOOT:
|
||||
if (conf->fixup_scsi)
|
||||
onboard_scsi_fixup();
|
||||
// if (conf->fixup_scsi)
|
||||
// onboard_scsi_fixup();
|
||||
// if (conf->fixup_vga)
|
||||
// vga_fixup();
|
||||
printk_debug("mainboard fixup pass %d done\r\n",
|
||||
pass);
|
||||
// printk_debug("mainboard fixup pass %d done\r\n",pass);
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1,4 +1,5 @@
|
|||
#define ASSEMBLY 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
|
|
@ -42,11 +43,12 @@ static void soft_reset(void)
|
|||
static void memreset_setup(void)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
} else {
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
|
|
@ -82,20 +84,21 @@ static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
|||
* [3] Route to Link 2
|
||||
*/
|
||||
|
||||
uint32_t ret = 0x00010101; /* default row entry */
|
||||
uint32_t ret=0x00010101; /* default row entry */
|
||||
|
||||
static const unsigned int rows_2p[2][2] = {
|
||||
{ 0x00050101, 0x00010404 },
|
||||
{ 0x00010404, 0x00050101 }
|
||||
};
|
||||
|
||||
if (maxnodes > 2) {
|
||||
if(maxnodes>2) {
|
||||
print_debug("this mainboard is only designed for 2 cpus\r\n");
|
||||
maxnodes = 2;
|
||||
maxnodes=2;
|
||||
}
|
||||
|
||||
if (!(node >= maxnodes || row >= maxnodes)) {
|
||||
ret = rows_2p[node][row];
|
||||
|
||||
if (!(node>=maxnodes || row>=maxnodes)) {
|
||||
ret=rows_2p[node][row];
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -147,10 +150,10 @@ static void main(void)
|
|||
#endif
|
||||
};
|
||||
|
||||
#if 1
|
||||
static const struct ht_chain ht_c[] = {
|
||||
{
|
||||
.udev = PCI_DEV(0, 0x18, 0),
|
||||
/* LDT2 */
|
||||
.upos = 0xc0,
|
||||
.devreg = 0xe0,
|
||||
},
|
||||
|
|
@ -160,27 +163,28 @@ static void main(void)
|
|||
.devreg = 0xe4,
|
||||
},
|
||||
};
|
||||
int needs_reset;
|
||||
#endif
|
||||
|
||||
int needs_reset;
|
||||
enable_lapic();
|
||||
init_timer();
|
||||
|
||||
if (cpu_init_detected()) {
|
||||
asm("jmp __cpu_reset");
|
||||
}
|
||||
|
||||
distinguish_cpu_resets();
|
||||
if (!boot_cpu()) {
|
||||
stop_this_cpu();
|
||||
}
|
||||
|
||||
w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
setup_s2885_resource_map();
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
#if 0
|
||||
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xc0);
|
||||
#else
|
||||
needs_reset |= ht_setup_chains(ht_c, sizeof(ht_c)/sizeof(ht_c[0]));
|
||||
#endif
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
|
|
@ -189,22 +193,20 @@ static void main(void)
|
|||
dump_pci_devices();
|
||||
#endif
|
||||
|
||||
|
||||
#if 0
|
||||
print_pci_devices();
|
||||
#endif
|
||||
|
||||
enable_smbus();
|
||||
|
||||
#if 0
|
||||
dump_spd_registers(&cpu[0]);
|
||||
#endif
|
||||
|
||||
memreset_setup();
|
||||
sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
|
||||
|
||||
#if 0
|
||||
dump_pci_devices();
|
||||
#endif
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 0x18, 1));
|
||||
#endif
|
||||
|
||||
|
|
@ -216,7 +218,11 @@ static void main(void)
|
|||
print_debug_hex32(msr.hi);
|
||||
print_debug_hex32(msr.lo);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
/*
|
||||
#if 0
|
||||
ram_check(0x00000000, msr.lo+(msr.hi<<32));
|
||||
#else
|
||||
#if TOTAL_CPUS < 2
|
||||
// Check 16MB of memory @ 0
|
||||
ram_check(0x00000000, 0x00100000);
|
||||
|
|
@ -225,4 +231,5 @@ static void main(void)
|
|||
ram_check(0x80000000, 0x80100000);
|
||||
#endif
|
||||
#endif
|
||||
*/
|
||||
}
|
||||
|
|
|
|||
|
|
@ -20,16 +20,16 @@ const struct irq_routing_table intel_irq_routing_table = {
|
|||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x35, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
{0x03,(0x4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x06, 0|0, {{0x0, 0x0000}, {0x0, 0x0000}, {0x0, 0x0000}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x01, 0|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
|
||||
{0x05,(0x3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x05,(0x6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x04,(0x8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x04,(0x7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x06,(0xa<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x04,(0x9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x06,(0xb<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x06,(0xc<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{3,(4<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x6,0, {{0, 0}, {0, 0}, {0, 0}, {0x4, 0xdef8}}, 0, 0},
|
||||
{0x1,0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0, 0}, {0, 0}}, 0x0, 0},
|
||||
{0x5,(3<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x1, 0},
|
||||
{0x5,(6<<3)|0, {{0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}}, 0x2, 0},
|
||||
{0x4,(8<<3)|0, {{0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}}, 0x3, 0},
|
||||
{0x4,(7<<3)|0, {{0x3, 0xdef8}, {0x4, 0xdef8}, {0x1, 0xdef8}, {0x2, 0xdef8}}, 0x4, 0},
|
||||
{0x6,(0x0a<<3)|0, {{0x1, 0xdef8}, {0x2, 0xdef8}, {0x3, 0xdef8}, {0x4, 0xdef8}}, 0x5, 0},
|
||||
{0x4,(9<<3)|0, {{0x1, 0xdef8}, {2, 0xdef8}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0b<<3)|0, {{0x2, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
{0x6,(0x0c<<3)|0, {{0x4, 0xdef8}, {0, 0}, {0, 0}, {0, 0}}, 0, 0},
|
||||
}
|
||||
};
|
||||
|
|
|
|||
|
|
@ -87,10 +87,11 @@ static void amd8111_enable_rom(void)
|
|||
pci_write_config8(dev, 0x43, byte);
|
||||
}
|
||||
#endif
|
||||
#if 0
|
||||
static void onboard_scsi_fixup(void)
|
||||
{
|
||||
struct device *dev;
|
||||
#if 0
|
||||
#if 1
|
||||
unsigned char i,j,k;
|
||||
|
||||
for(i=0;i<=6;i++) {
|
||||
|
|
@ -119,6 +120,7 @@ static void onboard_scsi_fixup(void)
|
|||
// print_mem();
|
||||
// amd8111_enable_rom();
|
||||
}
|
||||
#endif
|
||||
#if 0
|
||||
static void vga_fixup(void) {
|
||||
// we do this right here because:
|
||||
|
|
@ -153,8 +155,8 @@ enable(struct chip *chip, enum chip_pass pass)
|
|||
// case CONF_PASS_PRE_PCI:
|
||||
// case CONF_PASS_POST_PCI:
|
||||
case CONF_PASS_PRE_BOOT:
|
||||
if (conf->fixup_scsi)
|
||||
onboard_scsi_fixup();
|
||||
// if (conf->fixup_scsi)
|
||||
// onboard_scsi_fixup();
|
||||
// if (conf->fixup_vga)
|
||||
// vga_fixup();
|
||||
printk_debug("mainboard fixup pass %d done\r\n",
|
||||
|
|
|
|||
|
|
@ -13,12 +13,12 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
|
||||
unsigned char bus_num;
|
||||
unsigned char bus_isa;
|
||||
unsigned char bus_8111_0;
|
||||
unsigned char bus_8111_1;
|
||||
unsigned char bus_8131_1;
|
||||
unsigned char bus_8131_2;
|
||||
unsigned char bus_8111_1;
|
||||
unsigned char bus_8151_1;
|
||||
|
||||
|
||||
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
|
||||
memset(mc, 0, sizeof(*mc));
|
||||
|
||||
|
|
@ -44,31 +44,37 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
/* 8111 */
|
||||
dev = dev_find_slot(3, PCI_DEVFN(0x03,0));
|
||||
if (dev) {
|
||||
bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
|
||||
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
|
||||
bus_isa++;
|
||||
printk_debug("bus_isa=%d\n",bus_isa);
|
||||
} else {
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 3:03.0, using defaults\n");
|
||||
|
||||
bus_8111_1 = 6;
|
||||
bus_isa = 7;
|
||||
}
|
||||
|
||||
/* 8131-1 */
|
||||
dev = dev_find_slot(3, PCI_DEVFN(0x01,0));
|
||||
if (dev) {
|
||||
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 3:01.0, using defaults\n");
|
||||
|
||||
bus_8131_1 = 4;
|
||||
}
|
||||
/* 8131-2 */
|
||||
dev = dev_find_slot(3, PCI_DEVFN(0x02,0));
|
||||
if (dev) {
|
||||
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
} else {
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 3:02.0, using defaults\n");
|
||||
|
||||
bus_8131_2 = 5;
|
||||
}
|
||||
/* 8151 */
|
||||
|
|
@ -76,32 +82,37 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
if (dev) {
|
||||
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
|
||||
printk_debug("bus_8151_1=%d\n",bus_8151_1);
|
||||
} else {
|
||||
|
||||
}
|
||||
else {
|
||||
printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
|
||||
|
||||
bus_8151_1 = 2;
|
||||
}
|
||||
|
||||
|
||||
}
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
|
||||
|
||||
/*Bus: Bus ID Type*/
|
||||
/* define bus and isa numbers */
|
||||
for (bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
for(bus_num = 0; bus_num < bus_isa; bus_num++) {
|
||||
smp_write_bus(mc, bus_num, "PCI ");
|
||||
}
|
||||
smp_write_bus(mc, bus_isa, "ISA ");
|
||||
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
/*I/O APICs: APIC ID Version State Address*/
|
||||
smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
|
||||
{
|
||||
struct pci_dev *dev;
|
||||
uint32_t base;
|
||||
/* 8131-1 APIC */
|
||||
dev = dev_find_slot(3, PCI_DEVFN(0x1,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
base &= PCI_BASE_ADDRESS_MEM_MASK;
|
||||
smp_write_ioapic(mc, 3, 0x11, base);
|
||||
}
|
||||
/* 8131-2 APIC */
|
||||
dev = dev_find_slot(3, PCI_DEVFN(0x2,1));
|
||||
if (dev) {
|
||||
base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
|
||||
|
|
@ -110,8 +121,8 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
}
|
||||
}
|
||||
|
||||
/* ISA Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
|
||||
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#
|
||||
*/ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x1, 0x2, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, 0x2, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x3, 0x2, 0x3);
|
||||
|
|
@ -124,61 +135,56 @@ void *smp_write_config_table(void *v, unsigned long * processor_map)
|
|||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xd, 0x2, 0xd);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xe, 0x2, 0xe);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0xf, 0x2, 0xf);
|
||||
//??? What
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (4<<2)|3, 0x2, 0x13);
|
||||
//Onboard AMD AC97 Audio ???
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 0x3, (4<<2)|1, 0x2, 0x11);
|
||||
// Onboard AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0<<2)|3, 0x2, 0x13);
|
||||
|
||||
/* PCI Ints: Type Polarity Trigger Bus ID PCIDEVNUM|IRQ APIC ID PIN# */
|
||||
// Integrated SMBus 2.0
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|3, 0x2, 0x13);
|
||||
// Integrated AMD AC97 Audio
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_0, (0x04<<2)|1, 0x2, 0x11);
|
||||
|
||||
// Integrated AMD USB
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x00<<2)|3, 0x2, 0x13);
|
||||
|
||||
// Onboard Serial ATA
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11);
|
||||
// Onboard Firewire
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13);
|
||||
|
||||
// Onboard Broadcom NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x09<<2)|0, 0x3, 0x0);
|
||||
|
||||
// AGP Display Adapter
|
||||
// AGP Display Adapter
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8151_1, 0x0, 0x2, 0x10);
|
||||
|
||||
//Slot 5 PCI 32
|
||||
// Onboard Serial ATA
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0b<<2)|0, 0x2, 0x11);
|
||||
//Onboard Firewire
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0c<<2)|0, 0x2, 0x13);
|
||||
//Onboard Broadcom NIC
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (9<<2)|0, 0x3, 0x0);
|
||||
|
||||
//Slot 5 PCI 32
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|0, 0x2, 0x10);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|1, 0x2, 0x11);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|2, 0x2, 0x12); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8111_1, (0x0a<<2)|3, 0x2, 0x13); //
|
||||
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|0, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|1, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|2, 0x3, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x08<<2)|3, 0x3, 0x2);
|
||||
//Slot 3 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|0, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|1, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|2, 0x3, 0x1);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (8<<2)|3, 0x3, 0x2);//
|
||||
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|0, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|1, 0x3, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|2, 0x3, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (0x07<<2)|3, 0x3, 0x1);
|
||||
//Slot 4 PCIX 100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|0, 0x3, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|1, 0x3, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|2, 0x3, 0x0);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_1, (7<<2)|3, 0x3, 0x1);//
|
||||
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|0, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|1, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|2, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x03<<2)|3, 0x4, 0x3);
|
||||
//Slot 1 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|0, 0x4, 0x0);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|1, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|2, 0x4, 0x2); //
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (3<<2)|3, 0x4, 0x3); //
|
||||
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|0, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|1, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|2, 0x4, 0x3);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (0x06<<2)|3, 0x4, 0x0);
|
||||
//Slot 2 PCI-X 133/100/66
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|0, 0x4, 0x1);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|1, 0x4, 0x2);
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|2, 0x4, 0x3);//
|
||||
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_8131_2, (6<<2)|3, 0x4, 0x0);//
|
||||
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
|
||||
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
|
||||
smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
|
||||
smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
|
||||
|
||||
/* There is no extension information... */
|
||||
|
||||
/* Compute the checksums */
|
||||
|
|
|
|||
|
|
@ -33,9 +33,9 @@ default LB_CKS_RANGE_END=122
|
|||
default LB_CKS_LOC=123
|
||||
|
||||
driver mainboard.o
|
||||
driver lsi_scsi.o
|
||||
dir ../common/lsi_scsi
|
||||
#driver adaptec_scsi.o
|
||||
driver si_sata.o
|
||||
#driver si_sata.o
|
||||
#driver intel_nic.o
|
||||
#object reset.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
|
|
@ -116,9 +116,6 @@ mainboardinit cpu/i386/bist32_fail.inc
|
|||
###
|
||||
### Romcc output
|
||||
###
|
||||
#makerule ./failover.E dep "$(MAINBOARD)/failover.c" act "$(CPP) -I$(TOP)/src $(CPPFLAGS) $(MAINBOARD)/failover.c > ./failever.E"
|
||||
#makerule ./failover.inc dep "./romcc ./failover.E" act "./romcc -O ./failover.E > failover.inc"
|
||||
#mainboardinit .failover.inc
|
||||
|
||||
makerule ./failover.E
|
||||
depends "$(MAINBOARD)/failover.c"
|
||||
|
|
@ -136,7 +133,6 @@ end
|
|||
makerule ./auto.inc
|
||||
depends "./romcc ./auto.E"
|
||||
action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
|
||||
# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
|
||||
end
|
||||
mainboardinit cpu/k8/enable_mmx_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
|
|
|||
|
|
@ -40,24 +40,24 @@ static void soft_reset(void)
|
|||
}
|
||||
|
||||
|
||||
#define REV_B_RESET 0
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
#if REV_B_RESET==1
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
#else
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
#endif
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
#if REV_B_RESET==1
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
#endif
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||
|
|
|
|||
|
|
@ -34,9 +34,9 @@ default LB_CKS_RANGE_END=122
|
|||
default LB_CKS_LOC=123
|
||||
|
||||
driver mainboard.o
|
||||
driver lsi_scsi.o
|
||||
dir ../common/lsi_scsi
|
||||
#driver adaptec_scsi.o
|
||||
driver si_sata.o
|
||||
#driver si_sata.o
|
||||
#driver intel_nic.o
|
||||
#object reset.o
|
||||
if HAVE_MP_TABLE object mptable.o end
|
||||
|
|
@ -137,7 +137,6 @@ end
|
|||
makerule ./auto.inc
|
||||
depends "./romcc ./auto.E"
|
||||
action "./romcc -O2 -mcpu=k8 -o auto.inc --label-prefix=auto ./auto.E"
|
||||
# action "./romcc -mcpu=k8 -O ./auto.E > auto.inc"
|
||||
end
|
||||
mainboardinit cpu/k8/enable_mmx_sse.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
|
|
|||
|
|
@ -40,24 +40,24 @@ static void soft_reset(void)
|
|||
}
|
||||
|
||||
|
||||
#define REV_B_RESET 0
|
||||
static void memreset_setup(void)
|
||||
{
|
||||
#if REV_B_RESET==1
|
||||
if (is_cpu_pre_c0()) {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
|
||||
#else
|
||||
}
|
||||
else {
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
|
||||
#endif
|
||||
}
|
||||
outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
|
||||
}
|
||||
|
||||
static void memreset(int controllers, const struct mem_controller *ctrl)
|
||||
{
|
||||
if (is_cpu_pre_c0()) {
|
||||
udelay(800);
|
||||
#if REV_B_RESET==1
|
||||
outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
|
||||
#endif
|
||||
udelay(90);
|
||||
}
|
||||
}
|
||||
|
||||
static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
|
||||
|
|
@ -215,11 +215,8 @@ static void main(void)
|
|||
setup_s4882_resource_map();
|
||||
needs_reset = setup_coherent_ht_domain();
|
||||
needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0xa0);
|
||||
#if 0
|
||||
dump_pci_device(PCI_DEV(0, 4, 0));
|
||||
#endif
|
||||
if (needs_reset) {
|
||||
print_info("ht reset -");
|
||||
print_info("ht reset -\r\n");
|
||||
soft_reset();
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue