Lots of lx fixes. CLeanup mainly. THings now build
Signed-off-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2430 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
Ronald G. Minnich
parent
e8bfbb387c
commit
2ad85dbc65
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@ -904,6 +904,13 @@ define CONFIG_PCI_64BIT_PREF_MEM
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comment "allow PCI device get 4G above Region as pref mem"
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end
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define CONFIG_VIDEO_MB
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default none
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export used
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comment "Integrated graphics with UMA has dynamic setup"
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end
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###############################################
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# Board specific options
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@ -134,10 +134,10 @@ chip northbridge/amd/lx
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device pci 1.0 on end # Host Bridge
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chip drivers/pci/realmode
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device pci 1.1 on end # VGA
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register "rom_address" = "0xfffc0000" # at the beginning of 256k
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end
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# chip drivers/pci/realmode
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# device pci 1.1 on end # VGA
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# register "rom_address" = "0xfffc0000" # at the beginning of 256k
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# end
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device pci 1.2 off end # AES
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chip southbridge/amd/cs5536_lx
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@ -184,10 +184,10 @@ chip northbridge/amd/lx
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device pci f.6 off end # UDC controller
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device pci f.7 off end # OTG controller
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end
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chip drivers/pci/rtl8139
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device pci d.0 on end # Realtek LAN
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register "nic_irq" = "10"
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end
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# chip drivers/pci/rtl8139
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## device pci d.0 on end # Realtek LAN
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# register "nic_irq" = "10"
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# end
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end
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end
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@ -126,7 +126,7 @@ config chip.h
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chip northbridge/amd/lx
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# they keep changing this. 0:f.0 5c.w to see where it is
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register "irqmap" = "0xbaba"
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register "setupflash" = "1"
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register "setupflash" = "0"
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device apic_cluster 0 on
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chip cpu/amd/model_lx
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device apic 0 on end
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@ -136,21 +136,44 @@ chip northbridge/amd/lx
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device pci 1.0 on end
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device pci 1.1 on end
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chip southbridge/amd/cs5536_lx
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register "enable_gpio0_inta" = "1"
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register "enable_ide_nand_flash" = "0"
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register "enable_uarta" = "1"
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register "audio_irq" = "11"
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register "usbf4_irq" = "11"
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register "usbf11_irq" = "11"
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register "usbf6_irq" = "11"
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register "usbf7_irq" = "11"
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device pci d.0 on end # EEPRO 1000
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register "isa_irq" = "0"
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#register "flash_irq" = "14"
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## IDE IRQ
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register "enable_ide_irq" = "0"
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register "audio_irq" = "5"
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register "usb_irq" = "7"
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register "uart0_irq" = "0"
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register "uart1_irq" = "4"
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## PCI INTA ... INTD and their GPIO pins
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## int==0: disable
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register "pci_int[0]" = "0"
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register "pci_int[1]" = "10"
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register "pci_int[2]" = "0"
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register "pci_int[3]" = "0"
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register "pci_int_pin[0]" = "0"
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register "pci_int_pin[1]" = "7"
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register "pci_int_pin[2]" = "0"
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register "pci_int_pin[3]" = "0"
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# Keyboard Emulation Logic IRQs
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# Enable keyboard IRQ2
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register "enable_kel_keyb_irq" = "0"
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# Enable mouse IRQ12
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register "enable_kel_mouse_irq" = "0"
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# Configure KEL Emulation IRQ, 0 to disable
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register "kel_emul_irq" = "0"
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device pci f.0 on end # ISA Bridge
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device pci f.2 on end # IDE Controller
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device pci f.1 on end # Flash controller
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device pci f.2 off end # IDE controller
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device pci f.3 on end # Audio
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device pci f.4 on end # OHCI
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device pci f.5 on end # EHCI
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register "unwanted_vpci[0]" = "0" # End of list has a zero
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end
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end
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end
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@ -40,14 +40,21 @@ uses TTYS0_BASE
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uses TTYS0_LCS
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uses CONFIG_UDELAY_TSC
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uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
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uses CONFIG_CONSOLE_VGA
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uses CONFIG_PCI_ROM_RUN
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uses CONFIG_VIDEO_MB
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default CONFIG_VIDEO_MB=8
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## ROM_SIZE is the size of boot ROM that this board will use.
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default ROM_SIZE = 256*1024
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default ROM_SIZE = 1024*1024
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###
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### Build options
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###
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#default CONFIG_CONSOLE_VGA=1
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#default CONFIG_PCI_ROM_RUN=0
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##
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## Build code for the fallback boot
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##
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@ -39,22 +39,6 @@ static inline unsigned int fls(unsigned int x)
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/* sdram parameters for OLPC:
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row address = 13
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col address = 9
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banks = 4
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dimm0size=128MB
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d0_MB=1 (module banks)
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d0_cb=4 (component banks)
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do_psz=4KB (page size)
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Trc=10 (clocks) (ref2act)
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Tras=7 (act2pre)
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Trcd=3 (act2cmd)
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Trp=3 (pre2act)
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Trrd=2 (act2act)
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Tref=17.8ms
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*/
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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/* Total size of DIMM = 2^row address (byte 3) * 2^col address (byte 4) *
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@ -66,48 +50,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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unsigned char module_banks, val;
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#if 0 //GX3
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msr = rdmsr(MC_CF07_DATA);
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/* get module banks (sides) per dimm, SPD byte 5 */
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module_banks = 1;
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module_banks >>= 1;
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msr.hi &= ~(1 << CF07_UPPER_D0_MB_SHIFT);
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msr.hi |= (module_banks << CF07_UPPER_D0_MB_SHIFT);
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/* get component banks per module bank, SPD byte 17 */
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val = 4;
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val >>= 2;
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msr.hi &= ~(0x1 << CF07_UPPER_D0_CB_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_CB_SHIFT);
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/* get the module bank density, SPD byte 31 */
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/* this is multiples of 8 MB */
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/* actually it is 2^x*4, where x is the value you put in */
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/* for OLPC, set default size */
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/* dimm size - hardcoded 128Mb */
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val = 5;
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msr.hi &= ~(0xf << CF07_UPPER_D0_SZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_SZ_SHIFT);
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/* page size = 2^col address */
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val = 2; /* 4096 bytes */
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msr.hi &= ~(0x7 << CF07_UPPER_D0_PSZ_SHIFT);
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msr.hi |= (val << CF07_UPPER_D0_PSZ_SHIFT);
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print_debug("computed msr.hi ");
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print_debug_hex32(msr.hi);
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print_debug("\r\n");
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/* this is a standard value, DOES NOT PROBABLY MATCH FROM ABOVE */
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/* well, it may be close. It's about 200,000 ticks */
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msr.lo = 0x00003000;
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wrmsr(MC_CF07_DATA, msr);
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#endif
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msr.hi = 0x00005012;
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msr.lo = 0x05000040;
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msr.hi = 0x10075012;
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msr.lo = 0x00000040;
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wrmsr(MC_CF07_DATA, msr); //GX3
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@ -140,16 +84,16 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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#include "northbridge/amd/lx/raminit.c"
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#include "sdram/generic_sdram.c"
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#define PLLMSRhi 0x00001490
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#define PLLMSRlo 0x02000030
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#define PLLMSRlo1 ((0xde << 16) | (1 << 26) | (1 << 24))
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#define PLLMSRlo2 ((1<<14) |(1<<13) | (1<<0))
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/* CPU and GLIU mult/div */
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#define PLLMSRhi 0x0000039C
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/* Hold Count - how long we will sit in reset */
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#define PLLMSRlo 0x00DE0000
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#include "northbridge/amd/lx/pll_reset.c"
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#include "cpu/amd/model_lx/cpureginit.c"
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#include "cpu/amd/model_lx/syspreinit.c"
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static void msr_init(void)
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{
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__builtin_wrmsr(0x1808, 0x10f3bf00, 0x22fffc02);
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__builtin_wrmsr(0x10000020, 0xfff80, 0x20000000);
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__builtin_wrmsr(0x10000021, 0x80fffe0, 0x20000000);
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@ -4,8 +4,24 @@
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/lxdef.h>
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#include "chip.h"
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#define DIVIL_LBAR_GPIO 0x5140000c
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static void init_gpio()
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{
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msr_t msr;
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printk_debug("Initializing GPIO module...\n");
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// initialize the GPIO LBAR
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msr.lo = GPIO_BASE;
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msr.hi = 0x0000f001;
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wrmsr(DIVIL_LBAR_GPIO, msr);
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msr = rdmsr(DIVIL_LBAR_GPIO);
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printk_debug("DIVIL_LBAR_GPIO set to 0x%08x 0x%08x\n", msr.hi, msr.lo);
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}
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static void init(struct device *dev)
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{
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@ -17,6 +33,7 @@ static void init(struct device *dev)
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printk_debug("DIGITALLOGIC MSM800SSEV ENTER %s\n", __FUNCTION__);
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#if 0
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// FIXME: do we need to initialize USB OHCI this way?
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printk_debug("%s (%x,%x) set USB PCI interrupt line to %d\n",
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__FUNCTION__, bus, devUsb, irqUsb);
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@ -33,6 +50,8 @@ static void init(struct device *dev)
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nic = dev_find_slot(bus, devNic);
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if (!nic) printk_err("Could not find USB\n");
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else pci_write_config8(nic, PCI_INTERRUPT_LINE, irqNic);
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#endif
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init_gpio();
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printk_debug("DIGITALLOGIC MSM800SSEV EXIT %s\n", __FUNCTION__);
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}
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@ -47,7 +47,7 @@ void graphics_init(void)
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* External Monochrome Card Support(12) 0, NO
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* Controller Priority Select(11) 1, Primary
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* Display Select(10:8) 0x0, CRT
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* Graphics Memory Size(7:1) VIDEO_MB >> 1,
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* Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1,
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* defined in mainboard/../Options.lb
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* PLL Reference Clock Bypass(0) 0, Default
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*/
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@ -57,7 +57,7 @@ void graphics_init(void)
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* so we can add the real value in megabytes
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*/
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wData = 0x0800 | (VIDEO_MB & VG_MEM_MASK);
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wData = 0x0800 | (CONFIG_VIDEO_MB & VG_MEM_MASK);
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vrWrite(wClassIndex, wData);
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res = vrRead(wClassIndex);
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@ -521,7 +521,7 @@ static void pci_domain_set_resources(device_t dev)
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/* Report the memory regions */
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idx = 10;
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ram_resource(dev, idx++, 0, 640);
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ram_resource(dev, idx++, 1024, ((sizeram() - VIDEO_MB) * 1024) - SMM_SIZE - 1024);
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ram_resource(dev, idx++, 1024, ((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024);
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}
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assign_resources(&dev->link[0]);
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@ -1,11 +1,11 @@
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#ifndef _SOUTHBRIDGE_AMD_CS5536
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#define _SOUTHBRIDGE_AMD_CS5536
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#ifndef _SOUTHBRIDGE_AMD_CS5536_LX
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#define _SOUTHBRIDGE_AMD_CS5536_LX
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#define MAX_UNWANTED_VPCI 10 /* increase if needed */
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extern struct chip_operations southbridge_amd_cs5536_ops;
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extern struct chip_operations southbridge_amd_cs5536_lx_ops;
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struct southbridge_amd_cs5536_config {
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struct southbridge_amd_cs5536_lx_config {
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/* interrupt enable for LPC bus */
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int lpc_serirq_enable; /* how to enable, e.g. 0x80 */
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int lpc_irq; /* what to enable, e.g. 0x18 */
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@ -50,4 +50,4 @@ struct southbridge_amd_cs5536_config {
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unsigned long unwanted_vpci[MAX_UNWANTED_VPCI];
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};
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#endif /* _SOUTHBRIDGE_AMD_CS5536 */
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#endif /* _SOUTHBRIDGE_AMD_CS5536_LX */
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@ -158,7 +158,7 @@ void map_gpio_irq(unsigned int pin, unsigned int gpioirq, unsigned int irq, unsi
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static void southbridge_init(struct device *dev)
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{
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struct southbridge_amd_cs5536_config *sb = (struct southbridge_amd_cs5536_config *)dev->chip_info;
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struct southbridge_amd_cs5536_lx_config *sb = (struct southbridge_amd_cs5536_lx_config *)dev->chip_info;
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msr_t msr;
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int i;
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@ -316,14 +316,14 @@ static struct device_operations southbridge_ops = {
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.scan_bus = scan_static_bus,
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};
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static struct pci_driver cs5536_pci_driver __pci_driver = {
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static struct pci_driver cs5536_lx_pci_driver __pci_driver = {
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.ops = &southbridge_ops,
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.vendor = PCI_VENDOR_ID_AMD,
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.device = PCI_DEVICE_ID_AMD_CS5536_ISA
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};
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struct chip_operations southbridge_amd_cs5536_ops = {
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CHIP_NAME("AMD cs5536")
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struct chip_operations southbridge_amd_cs5536_lx_ops = {
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CHIP_NAME("AMD cs5536 (LX)")
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/* This only called when this device is listed in the
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* static device tree.
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*/
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@ -8,7 +8,7 @@ option CONFIG_COMPRESSED_ROM_STREAM_NRV2B=0
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## ROM_SIZE is the total number of bytes allocated for LinuxBIOS use
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## (normal AND fallback images and payloads).
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## leave 64k for vsa and 32K for video ROM
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option ROM_SIZE = 1024*256 - 64*1024 - 32 * 1024
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option ROM_SIZE = 1024*1024 - 64*1024 - 32 * 1024
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## ROM_IMAGE_SIZE is the maximum number of bytes allowed for a LinuxBIOS image,
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## not including any payload.
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