apollolake: update processor power limits configuration
Update processor power limit configuration parameters based on common code base support for Intel Apollo Lake SoC based platforms. BRANCH=None BUG=None TEST=Built and tested on octopus system Change-Id: I609744d165a53c8f91e42a67da1b972de00076a5 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41233 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -42,12 +42,14 @@ chip soc/intel/apollolake
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register "gpe0_dw2" = "PMC_GPE_N_95_64"
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register "gpe0_dw3" = "PMC_GPE_N_63_32"
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# PL1 override 10000 mW: Due to error in the energy calculation for
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# PL1 override 10 W: Due to error in the energy calculation for
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# current VR solution. Experiments show that SoC TDP max (6W) can
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# be reached when RAPL PL1 is set to 10W.
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register "tdp_pl1_override_mw" = "10000"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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register "power_limits_config" = "{
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.tdp_pl1_override = 10,
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.tdp_pl2_override = 15,
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}"
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# Minimum SLP S3 assertion width 28ms.
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register "slp_s3_assertion_width_usecs" = "28000"
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@ -52,12 +52,14 @@ chip soc/intel/apollolake
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# Enable DPTF
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register "dptf_enable" = "1"
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# PL1 override 12000 mW: the energy calculation is wrong with the
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# PL1 override 12 W: the energy calculation is wrong with the
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# current VR solution. Experiments show that SoC TDP max (6W) can
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# be reached when RAPL PL1 is set to 12W.
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register "tdp_pl1_override_mw" = "12000"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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register "power_limits_config" = "{
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.tdp_pl1_override = 12,
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.tdp_pl2_override = 15,
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}"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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@ -52,12 +52,14 @@ chip soc/intel/apollolake
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# Enable DPTF
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register "dptf_enable" = "1"
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# PL1 override 12000 mW: the energy calculation is wrong with the
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# PL1 override 12 W: the energy calculation is wrong with the
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# current VR solution. Experiments show that SoC TDP max (6W) can
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# be reached when RAPL PL1 is set to 12W.
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register "tdp_pl1_override_mw" = "12000"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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register "power_limits_config" = "{
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.tdp_pl1_override = 12,
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.tdp_pl2_override = 15,
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}"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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@ -52,12 +52,14 @@ chip soc/intel/apollolake
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# Enable DPTF
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register "dptf_enable" = "1"
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# PL1 override 12000 mW: the energy calculation is wrong with the
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# PL1 override 12 W: the energy calculation is wrong with the
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# current VR solution. Experiments show that SoC TDP max (6W) can
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# be reached when RAPL PL1 is set to 12W.
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register "tdp_pl1_override_mw" = "12000"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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register "power_limits_config" = "{
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.tdp_pl1_override = 12,
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.tdp_pl2_override = 15,
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}"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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@ -49,12 +49,14 @@ chip soc/intel/apollolake
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# Enable DPTF
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register "dptf_enable" = "1"
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# PL1 override 12000 mW: the energy calculation is wrong with the
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# PL1 override 12 W: the energy calculation is wrong with the
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# current VR solution. Experiments show that SoC TDP max (6W) can
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# be reached when RAPL PL1 is set to 12W.
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register "tdp_pl1_override_mw" = "12000"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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register "power_limits_config" = "{
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.tdp_pl1_override = 12,
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.tdp_pl2_override = 15,
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}"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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@ -52,12 +52,14 @@ chip soc/intel/apollolake
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# Enable DPTF
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register "dptf_enable" = "1"
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# PL1 override 12000 mW: the energy calculation is wrong with the
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# PL1 override 12 W: the energy calculation is wrong with the
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# current VR solution. Experiments show that SoC TDP max (6W) can
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# be reached when RAPL PL1 is set to 12W.
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register "tdp_pl1_override_mw" = "12000"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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register "power_limits_config" = "{
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.tdp_pl1_override = 12,
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.tdp_pl2_override = 15,
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}"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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@ -56,9 +56,11 @@ chip soc/intel/apollolake
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register "dptf_enable" = "1"
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# PL1 override: 7.5W setting gives a run-time 6W actual
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register "tdp_pl1_override_mw" = "7500"
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# Set RAPL PL2 to 15W.
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register "tdp_pl2_override_mw" = "15000"
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register "power_limits_config" = "{
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.tdp_pl1_override = 7,
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.tdp_pl2_override = 15,
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}"
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# Enable Audio Clock and Power gating
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register "hdaudio_clk_gate_enable" = "1"
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@ -61,6 +61,7 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_INTEL_COMMON
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select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
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select SOC_INTEL_COMMON_BLOCK
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select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
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select SOC_INTEL_COMMON_BLOCK_ACPI
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select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG
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select SOC_INTEL_COMMON_BLOCK_CPU
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@ -15,6 +15,7 @@
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#include <intelblocks/fast_spi.h>
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#include <intelblocks/msr.h>
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#include <intelblocks/p2sb.h>
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#include <intelblocks/power_limit.h>
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#include <intelblocks/xdci.h>
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#include <fsp/api.h>
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#include <fsp/util.h>
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@ -34,6 +35,7 @@
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#include <spi-generic.h>
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#include <timer.h>
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#include <soc/ramstage.h>
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#include <soc/soc_chip.h>
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#include "chip.h"
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@ -269,73 +271,6 @@ static void pcie_override_devicetree_after_silicon_init(void)
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pcie_update_device_tree(PCH_DEVFN_PCIE5, 2);
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}
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/* Configure package power limits */
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static void set_power_limits(void)
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{
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struct soc_intel_apollolake_config *cfg;
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msr_t rapl_msr_reg, limit;
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uint32_t power_unit;
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uint32_t tdp, min_power, max_power;
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uint32_t pl2_val;
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cfg = config_of_soc();
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if (CONFIG(APL_SKIP_SET_POWER_LIMITS)) {
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printk(BIOS_INFO, "Skip the RAPL settings.\n");
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return;
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}
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/* Get units */
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rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 1 << (rapl_msr_reg.lo & 0xf);
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/* Get power defaults for this SKU */
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rapl_msr_reg = rdmsr(MSR_PKG_POWER_SKU);
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tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
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pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
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min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
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max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
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if (min_power > 0 && tdp < min_power)
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tdp = min_power;
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if (max_power > 0 && tdp > max_power)
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tdp = max_power;
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/* Set PL1 override value */
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tdp = (cfg->tdp_pl1_override_mw == 0) ?
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tdp : (cfg->tdp_pl1_override_mw * power_unit) / 1000;
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/* Set PL2 override value */
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pl2_val = (cfg->tdp_pl2_override_mw == 0) ?
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pl2_val : (cfg->tdp_pl2_override_mw * power_unit) / 1000;
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/* Set long term power limit to TDP */
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limit.lo = tdp & PKG_POWER_LIMIT_MASK;
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/* Set PL1 Pkg Power clamp bit */
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limit.lo |= PKG_POWER_LIMIT_CLAMP;
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limit.lo |= PKG_POWER_LIMIT_EN;
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limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
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PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
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/* Set short term power limit PL2 */
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limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
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limit.hi |= PKG_POWER_LIMIT_EN;
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/* Program package power limits in RAPL MSR */
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wrmsr(MSR_PKG_POWER_LIMIT, limit);
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printk(BIOS_INFO, "RAPL PL1 %d.%dW\n", tdp / power_unit,
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100 * (tdp % power_unit) / power_unit);
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printk(BIOS_INFO, "RAPL PL2 %d.%dW\n", pl2_val / power_unit,
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100 * (pl2_val % power_unit) / power_unit);
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/* Setting RAPL MMIO register for Power limits.
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* RAPL driver is using MSR instead of MMIO.
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* So, disabled LIMIT_EN bit for MMIO. */
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MCHBAR32(MCHBAR_RAPL_PPL) = limit.lo & ~PKG_POWER_LIMIT_EN;
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MCHBAR32(MCHBAR_RAPL_PPL + 4) = limit.hi & ~PKG_POWER_LIMIT_EN;
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}
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/* Overwrites the SCI IRQ if another IRQ number is given by device tree. */
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static void set_sci_irq(void)
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{
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static void soc_init(void *data)
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{
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struct soc_power_limits_config *soc_config;
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config_t *config;
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/* Snapshot the current GPIO IRQ polarities. FSP is setting a
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* default policy that doesn't honor boards' requirements. */
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itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END);
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@ -384,8 +322,10 @@ static void soc_init(void *data)
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/* Allocate ACPI NVS in CBMEM */
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cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(struct global_nvs_t));
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/* Set RAPL MSR for Package power limits*/
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set_power_limits();
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config = config_of_soc();
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/* Set RAPL MSR for Package power limits */
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soc_config = &config->power_limits_config;
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set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
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/*
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* FSP-S routes SCI to IRQ 9. With the help of this function you can
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@ -9,6 +9,7 @@
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#include <intelblocks/lpc_lib.h>
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#include <intelblocks/power_limit.h>
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#include <device/i2c_simple.h>
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#include <drivers/i2c/designware/dw_i2c.h>
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#include <soc/pm.h>
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@ -28,6 +29,9 @@ struct soc_intel_apollolake_config {
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/* Common structure containing soc config data required by common code*/
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struct soc_intel_common_config common_soc_config;
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/* Common struct containing power limits configuration info */
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struct soc_power_limits_config power_limits_config;
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/*
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* Mapping from PCIe root port to CLKREQ input on the SOC. The SOC has
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* four CLKREQ inputs, but six root ports. Root ports without an
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@ -99,11 +103,6 @@ struct soc_intel_apollolake_config {
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/* TCC activation offset value in degrees Celsius */
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int tcc_offset;
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/* PL1 override value in mW for APL */
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uint16_t tdp_pl1_override_mw;
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/* PL2 override value in mW for APL */
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uint16_t tdp_pl2_override_mw;
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/* Configure Audio clk gate and power gate
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* IOSF-SB port ID 92 offset 0x530 [5] and [3]
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*/
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@ -0,0 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* This file is part of the coreboot project. */
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#ifndef _SOC_MSR_H_
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#define _SOC_MSR_H_
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#include <intelblocks/msr.h>
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#endif
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