GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel/cannonlake/Kconfig: Deduplicate selections 

All of the SoCs in the cannonlake directory select the following
options. So move them to the common option SOC_INTEL_CANNONLAKE_BASE
in order to deduplicate selections.

  * FSP_USES_CB_STACK
  * HAVE_INTEL_FSP_REPO
  * SOC_INTEL_CONFIGURE_DDI_A_4_LANES

Change-Id: I6ce5edb2ba2c138b44601b32c3ecba2e761136f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77447
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
This commit is contained in:
Felix Singer 2023-08-25 11:32:26 +02:00 committed by Felix Singer
parent 53adf21174
commit 2aeb6e405a
1 changed files with 3 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/soc/intel/cannonlake/Kconfig
View File

@ -13,11 +13,13 @@ config SOC_INTEL_CANNONLAKE_BASE
select FSP_COMPRESS_FSP_S_LZMA select FSP_COMPRESS_FSP_S_LZMA
select FSP_M_XIP select FSP_M_XIP
select FSP_STATUS_GLOBAL_RESET_REQUIRED_3 select FSP_STATUS_GLOBAL_RESET_REQUIRED_3
select FSP_USES_CB_STACK
select GENERIC_GPIO_LIB select GENERIC_GPIO_LIB
select HAVE_DPTF_EISA_HID select HAVE_DPTF_EISA_HID
select HAVE_FSP_GOP select HAVE_FSP_GOP
select HAVE_FSP_LOGO_SUPPORT select HAVE_FSP_LOGO_SUPPORT
select HAVE_HYPERTHREADING select HAVE_HYPERTHREADING
select HAVE_INTEL_FSP_REPO
select HAVE_SMI_HANDLER select HAVE_SMI_HANDLER
select IDT_IN_EVERY_STAGE select IDT_IN_EVERY_STAGE
select INTEL_DESCRIPTOR_MODE_CAPABLE select INTEL_DESCRIPTOR_MODE_CAPABLE
@ -58,6 +60,7 @@ config SOC_INTEL_CANNONLAKE_BASE
select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_NHLT
select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_PCH_CLIENT
select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_RESET
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION
select SSE2 select SSE2
select SUPPORT_CPU_UCODE_IN_CBFS select SUPPORT_CPU_UCODE_IN_CBFS
@ -72,30 +75,21 @@ config SOC_INTEL_CANNONLAKE_BASE
config SOC_INTEL_COFFEELAKE config SOC_INTEL_COFFEELAKE
bool bool
select SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_EXP_X86_64_SUPPORT select HAVE_EXP_X86_64_SUPPORT
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM select HECI_DISABLE_USING_SMM
select INTEL_CAR_NEM select INTEL_CAR_NEM
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_WHISKEYLAKE config SOC_INTEL_WHISKEYLAKE
bool bool
select SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM select HECI_DISABLE_USING_SMM
select INTEL_CAR_NEM_ENHANCED select INTEL_CAR_NEM_ENHANCED
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_COMETLAKE config SOC_INTEL_COMETLAKE
bool bool
select SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select INTEL_CAR_NEM_ENHANCED select INTEL_CAR_NEM_ENHANCED
select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BASECODE
select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_BASECODE_RAMTOP