security/vboot: Fix remaining measured boot issues
Makes vboot measured boot mode available for all boards. * Increase Tegra210 and Rockchip3228 SRAM for romstage/verstage. * Add missing files for Intel apollolake and AMD stoneyridge as TPM driver target. Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/29840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
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@ -87,6 +87,7 @@ postcar-$(CONFIG_STONEYRIDGE_UART) += uart.c
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postcar-y += ramtop.c
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postcar-y += ramtop.c
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postcar-y += sb_util.c
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postcar-y += sb_util.c
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postcar-y += nb_util.c
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postcar-y += nb_util.c
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postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += i2c.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += BiosCallOuts.c
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ramstage-y += i2c.c
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ramstage-y += i2c.c
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@ -75,6 +75,7 @@ postcar-y += i2c.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += heci.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
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postcar-$(CONFIG_RESET_ON_INVALID_RAMSTAGE_CACHE) += reset.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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postcar-$(CONFIG_UART_DEBUG) += uart.c
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postcar-$(CONFIG_VBOOT_MEASURED_BOOT) += gspi.c
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verstage-y += car.c
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verstage-y += car.c
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verstage-y += i2c.c
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verstage-y += i2c.c
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@ -28,18 +28,18 @@
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SECTIONS
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SECTIONS
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{
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{
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SRAM_START(0x40000000)
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SRAM_START(0x40000000)
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PRERAM_CBMEM_CONSOLE(0x40000000, 8K)
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PRERAM_CBMEM_CONSOLE(0x40000000, 4K)
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PRERAM_CBFS_CACHE(0x40002000, 36K)
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PRERAM_CBFS_CACHE(0x40001000, 36K)
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VBOOT2_WORK(0x4000B000, 12K)
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VBOOT2_WORK(0x4000A000, 12K)
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#if ENV_ARM64
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#if ENV_ARM64
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STACK(0x4000E000, 3K)
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STACK(0x4000D000, 3K)
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#else /* AVP gets a separate stack to avoid any chance of handoff races. */
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#else /* AVP gets a separate stack to avoid any chance of handoff races. */
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STACK(0x4000EC00, 3K)
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STACK(0x4000DC00, 3K)
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#endif
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#endif
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TIMESTAMP(0x4000F800, 2K)
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TIMESTAMP(0x4000E800, 2K)
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BOOTBLOCK(0x40010000, 28K)
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BOOTBLOCK(0x4000F000, 28K)
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VERSTAGE(0x40017000, 64K)
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VERSTAGE(0x40016000, 64K)
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ROMSTAGE(0x40027000, 100K)
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ROMSTAGE(0x40026000, 104K)
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SRAM_END(0x40040000)
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SRAM_END(0x40040000)
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DRAM_START(0x80000000)
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DRAM_START(0x80000000)
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@ -31,9 +31,9 @@ SECTIONS
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SRAM_START(0xFF700000)
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SRAM_START(0xFF700000)
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TTB(0xFF700000, 16K)
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TTB(0xFF700000, 16K)
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BOOTBLOCK(0xFF704004, 20K - 4)
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BOOTBLOCK(0xFF704004, 20K - 4)
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PRERAM_CBMEM_CONSOLE(0xFF709000, 3K)
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PRERAM_CBMEM_CONSOLE(0xFF709000, 2K)
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VBOOT2_WORK(0xFF709C00, 12K)
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VBOOT2_WORK(0xFF709800, 12K)
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OVERLAP_VERSTAGE_ROMSTAGE(0xFF70CC00, 41K)
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OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C800, 42K)
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PRERAM_CBFS_CACHE(0xFF717000, 1K)
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PRERAM_CBFS_CACHE(0xFF717000, 1K)
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TIMESTAMP(0xFF717400, 0x180)
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TIMESTAMP(0xFF717400, 0x180)
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STACK(0xFF717580, 3K - 0x180)
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STACK(0xFF717580, 3K - 0x180)
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