soc/intel/skylake: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers (maybe, who knows, the blob is undocu- mented), advertised to FSP and reserved from the OS. The new devicetree option `ignore_vtd` allows to retain the old beha- viour (do whatever pre-set UPD values suggest). We also let FSP set up distinct BDFs for messages originating from the I/O-APIC and the HPET. Change-Id: I77f87c385736615c127143760bbd144f97986b37 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/21597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
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@ -113,6 +113,9 @@ struct soc_intel_skylake_config {
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/* Estimated maximum platform power in Watts */
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u16 psys_pmax;
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/* Wether to ignore VT-d support of the SKU */
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int ignore_vtd;
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/*
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* The following fields come from FspUpdVpd.h.
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* These are configuration values that are passed to FSP during
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@ -31,9 +31,11 @@
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#include <soc/acpi.h>
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#include <soc/intel/common/vbt.h>
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#include <soc/interrupt.h>
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#include <soc/iomap.h>
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#include <soc/irq.h>
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#include <soc/pci_devs.h>
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#include <soc/ramstage.h>
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#include <soc/systemagent.h>
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#include <string.h>
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void soc_init_pre_device(void *chip_info)
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@ -326,6 +328,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
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/* Set TccActivationOffset */
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tconfig->TccActivationOffset = config->tcc_offset;
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/* Enable VT-d and X2APIC */
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if (!config->ignore_vtd && soc_is_vtd_capable()) {
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params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
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params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
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params->X2ApicOptOut = 0;
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tconfig->VtdDisable = 0;
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params->PchIoApicBdfValid = 1;
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params->PchIoApicBusNumber = 250;
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params->PchIoApicDeviceNumber = 31;
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params->PchIoApicFunctionNumber = 0;
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}
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soc_irq_settings(params);
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}
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@ -49,6 +49,12 @@
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#define GDXC_BASE_ADDRESS 0xfed84000
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#define GDXC_BASE_SIZE 0x1000
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#define GFXVT_BASE_ADDRESS 0xfed90000
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#define GFXVT_BASE_SIZE 0x1000
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#define VTVC0_BASE_ADDRESS 0xfed91000
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#define VTVC0_BASE_SIZE 0x1000
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#define HPET_BASE_ADDRESS 0xfed00000
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#define PCH_PWRM_BASE_ADDRESS 0xfe000000
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@ -32,9 +32,13 @@
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#define D_LCK (1 << 4)
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#define G_SMRAME (1 << 3)
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#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
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#define CAPID0_A 0xe4
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#define VTD_DISABLE (1 << 23)
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#define BIOS_RESET_CPL 0x5da8
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#define GFXVTBAR 0x5400
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#define EDRAMBAR 0x5408
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#define VTVC0BAR 0x5410
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#define GDXCBAR 0x5420
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#define MCH_PKG_POWER_LIMIT_LO 0x59a0
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@ -42,4 +46,11 @@
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#define MCH_DDR_POWER_LIMIT_LO 0x58e0
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#define MCH_DDR_POWER_LIMIT_HI 0x58e4
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bool soc_is_vtd_capable(void);
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static const struct sa_mmio_descriptor soc_vtd_resources[] = {
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{ GFXVTBAR, GFXVT_BASE_ADDRESS, GFXVT_BASE_SIZE, "GFXVTBAR" },
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{ VTVC0BAR, VTVC0_BASE_ADDRESS, VTVC0_BASE_SIZE, "VTVC0BAR" },
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};
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#endif
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@ -234,6 +234,13 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
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m_cfg->PcieRpEnableMask = mask;
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cpu_flex_override(m_cfg);
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if (!config->ignore_vtd) {
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m_cfg->PchHpetBdfValid = 1;
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m_cfg->PchHpetBusNumber = 250;
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m_cfg->PchHpetDeviceNumber = 15;
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m_cfg->PchHpetFunctionNumber = 0;
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}
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}
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void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
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@ -18,8 +18,28 @@
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#include <device/device.h>
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#include <intelblocks/systemagent.h>
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#include <soc/iomap.h>
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#include <soc/pci_devs.h>
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#include <soc/romstage.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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static void systemagent_vtd_init(void)
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{
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const struct device *const dev = dev_find_slot(0, SA_DEVFN_ROOT);
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const struct soc_intel_skylake_config *config = NULL;
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if (dev)
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config = dev->chip_info;
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if (config && config->ignore_vtd)
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return;
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const bool vtd_capable =
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!(pci_read_config32(SA_DEV_ROOT, CAPID0_A) & VTD_DISABLE);
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if (!vtd_capable)
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return;
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sa_set_mch_bar(soc_vtd_resources, ARRAY_SIZE(soc_vtd_resources));
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}
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void systemagent_early_init(void)
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{
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@ -40,6 +60,9 @@ void systemagent_early_init(void)
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/* Set Fixed MMIO address into MCH base address */
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sa_set_mch_bar(soc_fixed_mch_resources,
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ARRAY_SIZE(soc_fixed_mch_resources));
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systemagent_vtd_init();
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/* Enable PAM registers */
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enable_pam_region();
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}
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@ -15,6 +15,7 @@
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* GNU General Public License for more details.
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*/
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#include <arch/io.h>
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#include <cpu/x86/msr.h>
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#include <console/console.h>
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#include <delay.h>
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@ -23,7 +24,16 @@
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#include <soc/cpu.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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#include <soc/pci_devs.h>
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#include <soc/systemagent.h>
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#include "chip.h"
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bool soc_is_vtd_capable(void)
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{
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struct device *const root_dev = SA_DEV_ROOT;
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return root_dev &&
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!(pci_read_config32(root_dev, CAPID0_A) & VTD_DISABLE);
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}
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/*
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* SoC implementation
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@ -42,9 +52,14 @@ void soc_add_fixed_mmio_resources(struct device *dev, int *index)
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{ GDXCBAR, GDXC_BASE_ADDRESS, GDXC_BASE_SIZE, "GDXCBAR" },
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{ EDRAMBAR, EDRAM_BASE_ADDRESS, EDRAM_BASE_SIZE, "EDRAMBAR" },
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};
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const struct soc_intel_skylake_config *const config = dev->chip_info;
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sa_add_fixed_mmio_resources(dev, index, soc_fixed_resources,
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ARRAY_SIZE(soc_fixed_resources));
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if (!(config && config->ignore_vtd) && soc_is_vtd_capable())
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sa_add_fixed_mmio_resources(dev, index, soc_vtd_resources,
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ARRAY_SIZE(soc_vtd_resources));
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}
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/*
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