mb/intel/adlrvp: Set EPP to 45% for all Adl RVP variants

This sets EPP value to be 45% for all Adl RVP variants.

Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.

TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.

Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: If83a2148d596efccd2e50cc82f1afcbfb9ebb935
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>

src/mainboard/intel/adlrvp/devicetree.cb

@@ -168,6 +168,10 @@ chip soc/intel/alderlake
 
 	register "cnvi_bt_audio_offload" = "true"
 
+	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
+	register "enable_energy_perf_pref" = "true"
+	register "energy_perf_pref_value" = "0x73"
+
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.i2c[0] = {

src/mainboard/intel/adlrvp/devicetree_m.cb

@@ -143,6 +143,10 @@ chip soc/intel/alderlake
 	register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ"
 	register "pch_hda_idisp_codec_enable" = "1"
 
+	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
+	register "enable_energy_perf_pref" = "true"
+	register "energy_perf_pref_value" = "0x73"
+
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.gspi[1] = {

src/mainboard/intel/adlrvp/devicetree_n.cb

@@ -127,6 +127,10 @@ chip soc/intel/alderlake
 
 	register "cnvi_bt_audio_offload" = "true"
 
+	# set EPP to 45%: 45 * 256/100 = 115 = 0x73
+	register "enable_energy_perf_pref" = "true"
+	register "energy_perf_pref_value" = "0x73"
+
 	# Intel Common SoC Config
 	register "common_soc_config" = "{
 		.i2c[0] = {