intel/skylake: Add VrConfig UPD parameters from coreboot
Adding VrConfig UPDs and assign values to those from devicetree BRANCH=none BUG=chrome-os-partner:45387 TEST=Build and booted in kunimitsu CQ-DEPEND=CL:310192 Change-Id: Ifce9dfacabc742b55266c48459c56c69b1f22236 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b34a3cc77afc8795abb64972f8169986c30c2acd Original-Change-Id: Ifa960e718ed77db729f1fc4e2c00c9b305093e04 Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/311317 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/12944 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
This commit is contained in:
Rizwan Qureshi
Patrick Georgi
parent
b6319c1121
commit
2b1e8b3c3d
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@ -347,6 +347,29 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
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params->SkipMpInit = config->SkipMpInit;
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for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) {
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params->VrConfigEnable[i] =
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config->domain_vr_config[i].vr_config_enable;
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params->Psi1Threshold[i] =
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config->domain_vr_config[i].psi1threshold;
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params->Psi2Threshold[i] =
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config->domain_vr_config[i].psi2threshold;
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params->Psi3Threshold[i] =
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config->domain_vr_config[i].psi3threshold;
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params->Psi3Enable[i] =
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config->domain_vr_config[i].psi3enable;
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params->Psi4Enable[i] =
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config->domain_vr_config[i].psi4enable;
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params->ImonSlope[i] =
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config->domain_vr_config[i].imon_slope;
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params->ImonOffset[i] =
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config->domain_vr_config[i].imon_offset;
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params->IccMax[i] =
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config->domain_vr_config[i].icc_max;
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params->VrVoltageLimit[i] =
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config->domain_vr_config[i].voltage_limit;
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}
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/* Show SPI controller if enabled in devicetree.cb */
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dev = dev_find_slot(0, PCH_DEVFN_SPI);
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params->ShowSpiController = dev->enabled;
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@ -762,7 +785,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
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fsp_display_upd_value("TcoIrqEnable", 1,
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original->TcoIrqEnable,
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params->TcoIrqEnable);
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fsp_display_upd_value("LockDownConfigGlobalSmi", 1,
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original->LockDownConfigGlobalSmi,
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params->LockDownConfigGlobalSmi);
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@ -827,6 +849,156 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
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original->SerialIrqConfigStartFramePulse,
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params->SerialIrqConfigStartFramePulse);
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fsp_display_upd_value("Psi1Threshold[0]", 1,
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original->Psi1Threshold[0],
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params->Psi1Threshold[0]);
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fsp_display_upd_value("Psi1Threshold[1]", 1,
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original->Psi1Threshold[1],
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params->Psi1Threshold[1]);
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fsp_display_upd_value("Psi1Threshold[2]", 1,
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original->Psi1Threshold[2],
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params->Psi1Threshold[2]);
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fsp_display_upd_value("Psi1Threshold[3]", 1,
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original->Psi1Threshold[3],
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params->Psi1Threshold[3]);
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fsp_display_upd_value("Psi1Threshold[4]", 1,
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original->Psi1Threshold[4],
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params->Psi1Threshold[4]);
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fsp_display_upd_value("Psi2Threshold[0]", 1,
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original->Psi2Threshold[0],
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params->Psi2Threshold[0]);
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fsp_display_upd_value("Psi2Threshold[1]", 1,
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original->Psi2Threshold[1],
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params->Psi2Threshold[1]);
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fsp_display_upd_value("Psi2Threshold[2]", 1,
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original->Psi2Threshold[2],
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params->Psi2Threshold[2]);
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fsp_display_upd_value("Psi2Threshold[3]", 1,
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original->Psi2Threshold[3],
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params->Psi2Threshold[3]);
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fsp_display_upd_value("Psi2Threshold[4]", 1,
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original->Psi2Threshold[4],
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params->Psi2Threshold[4]);
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fsp_display_upd_value("Psi3Threshold[0]", 1,
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original->Psi3Threshold[0],
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params->Psi3Threshold[0]);
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fsp_display_upd_value("Psi3Threshold[1]", 1,
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original->Psi3Threshold[1],
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params->Psi3Threshold[1]);
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fsp_display_upd_value("Psi3Threshold[2]", 1,
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original->Psi3Threshold[2],
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params->Psi3Threshold[2]);
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fsp_display_upd_value("Psi3Threshold[3]", 1,
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original->Psi3Threshold[3],
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params->Psi3Threshold[3]);
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fsp_display_upd_value("Psi3Threshold[4]", 1,
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original->Psi3Threshold[4],
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params->Psi3Threshold[4]);
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fsp_display_upd_value("Psi3Enable[0]", 1,
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original->Psi3Enable[0],
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params->Psi3Enable[0]);
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fsp_display_upd_value("Psi3Enable[1]", 1,
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original->Psi3Enable[1],
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params->Psi3Enable[1]);
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fsp_display_upd_value("Psi3Enable[2]", 1,
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original->Psi3Enable[2],
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params->Psi3Enable[2]);
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fsp_display_upd_value("Psi3Enable[3]", 1,
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original->Psi3Enable[3],
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params->Psi3Enable[3]);
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fsp_display_upd_value("Psi3Enable[4]", 1,
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original->Psi3Enable[4],
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params->Psi3Enable[4]);
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fsp_display_upd_value("Psi4Enable[0]", 1,
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original->Psi4Enable[0],
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params->Psi4Enable[0]);
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fsp_display_upd_value("Psi4Enable[1]", 1,
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original->Psi4Enable[1],
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params->Psi4Enable[1]);
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fsp_display_upd_value("Psi4Enable[2]", 1,
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original->Psi4Enable[2],
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params->Psi4Enable[2]);
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fsp_display_upd_value("Psi4Enable[3]", 1,
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original->Psi4Enable[3],
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params->Psi4Enable[3]);
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fsp_display_upd_value("Psi4Enable[4]", 1,
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original->Psi4Enable[4],
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params->Psi4Enable[4]);
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fsp_display_upd_value("ImonSlope[0]", 1,
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original->ImonSlope[0],
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params->ImonSlope[0]);
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fsp_display_upd_value("ImonSlope[1]", 1,
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original->ImonSlope[1],
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params->ImonSlope[1]);
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fsp_display_upd_value("ImonSlope[2]", 1,
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original->ImonSlope[2],
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params->ImonSlope[2]);
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fsp_display_upd_value("ImonSlope[3]", 1,
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original->ImonSlope[3],
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params->ImonSlope[3]);
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fsp_display_upd_value("ImonSlope[4]", 1,
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original->ImonSlope[4],
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params->ImonSlope[4]);
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fsp_display_upd_value("ImonOffse[0]t", 1,
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original->ImonOffset[0],
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params->ImonOffset[0]);
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fsp_display_upd_value("ImonOffse[1]t", 1,
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original->ImonOffset[1],
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params->ImonOffset[1]);
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fsp_display_upd_value("ImonOffse[2]t", 1,
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original->ImonOffset[2],
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params->ImonOffset[2]);
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fsp_display_upd_value("ImonOffse[3]t", 1,
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original->ImonOffset[3],
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params->ImonOffset[3]);
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fsp_display_upd_value("ImonOffse[4]t", 1,
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original->ImonOffset[4],
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params->ImonOffset[4]);
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fsp_display_upd_value("IccMax[0]", 1,
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original->IccMax[0],
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params->IccMax[0]);
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fsp_display_upd_value("IccMax[1]", 1,
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original->IccMax[1],
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params->IccMax[1]);
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fsp_display_upd_value("IccMax[2]", 1,
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original->IccMax[2],
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params->IccMax[2]);
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fsp_display_upd_value("IccMax[3]", 1,
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original->IccMax[3],
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params->IccMax[3]);
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fsp_display_upd_value("IccMax[4]", 1,
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original->IccMax[4],
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params->IccMax[4]);
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fsp_display_upd_value("VrVoltageLimit[0]", 1,
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original->VrVoltageLimit[0],
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params->VrVoltageLimit[0]);
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fsp_display_upd_value("VrVoltageLimit[1]", 1,
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original->VrVoltageLimit[1],
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params->VrVoltageLimit[1]);
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fsp_display_upd_value("VrVoltageLimit[2]", 1,
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original->VrVoltageLimit[2],
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params->VrVoltageLimit[2]);
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fsp_display_upd_value("VrVoltageLimit[3]", 1,
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original->VrVoltageLimit[3],
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params->VrVoltageLimit[3]);
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fsp_display_upd_value("VrVoltageLimit[4]", 1,
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original->VrVoltageLimit[4],
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params->VrVoltageLimit[4]);
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fsp_display_upd_value("VrConfigEnable[0]", 1,
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original->VrConfigEnable[0],
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params->VrConfigEnable[0]);
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fsp_display_upd_value("VrConfigEnable[1]", 1,
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original->VrConfigEnable[1],
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params->VrConfigEnable[1]);
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fsp_display_upd_value("VrConfigEnable[2]", 1,
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original->VrConfigEnable[2],
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params->VrConfigEnable[2]);
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fsp_display_upd_value("VrConfigEnable[3]", 1,
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original->VrConfigEnable[3],
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params->VrConfigEnable[3]);
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fsp_display_upd_value("VrConfigEnable[4]", 1,
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original->VrConfigEnable[4],
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params->VrConfigEnable[4]);
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}
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static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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@ -25,6 +25,7 @@
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#include <soc/pmc.h>
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#include <soc/serialio.h>
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#include <soc/usb.h>
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#include <soc/vr_config.h>
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struct soc_intel_skylake_config {
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/*
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@ -325,6 +326,11 @@ struct soc_intel_skylake_config {
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*/
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u8 SerialIrqConfigStartFramePulse;
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u8 SkipMpInit;
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/* VrConfig Settings for 5 domains
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* 0 = System Agent, 1 = IA Core, 2 = Ring,
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* 3 = GT unsliced, 4 = GT sliced
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*/
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struct vr_config domain_vr_config[NUM_VR_DOMAINS];
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};
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typedef struct soc_intel_skylake_config config_t;
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@ -0,0 +1,77 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014 Google Inc.
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* Copyright (C) 2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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/* VR Settings for each domain */
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#ifndef _SOC_VR_CONFIG_H_
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#define _SOC_VR_CONFIG_H_
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struct vr_config {
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/*
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* The below settings will take effect when this is set to 1
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* for that domain.
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*/
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int vr_config_enable;
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/* Power State X current cuttof in 1/4 Amp increments
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* Range is 0-128A
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*/
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int psi1threshold;
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int psi2threshold;
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int psi3threshold;
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/* Enable power state 3/4 for different domains */
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int psi3enable;
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int psi4enable;
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/*
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* Imon slope correction. Specified in 1/100 increment
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* values. Range is 0-200. 125 = 1.25
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*/
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int imon_slope;
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/*
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* Imon offset correction. Units 1/4, Range 0-255.
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* Value of 100 = 100/4 = 25 offset.
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*/
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int imon_offset;
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/* VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A */
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int icc_max;
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/* VR Voltage Limit. Range is 0-7999mV */
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int voltage_limit;
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};
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/* VrConfig Settings for 5 domains
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* 0 = System Agent, 1 = IA Core, 2 = Ring,
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* 3 = GT unsliced, 4 = GT sliced
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*/
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enum vr_domain{
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VR_SYSTEM_AGENT,
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VR_IA_CORE,
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VR_RING,
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VR_GT_UNSLICED,
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VR_GT_SLICED,
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NUM_VR_DOMAINS
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};
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#endif
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