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intel/skylake: Add VrConfig UPD parameters from coreboot 

Adding VrConfig UPDs and assign values to those from devicetree

BRANCH=none
BUG=chrome-os-partner:45387
TEST=Build and booted in kunimitsu

CQ-DEPEND=CL:310192

Change-Id: Ifce9dfacabc742b55266c48459c56c69b1f22236
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b34a3cc77afc8795abb64972f8169986c30c2acd
Original-Change-Id: Ifa960e718ed77db729f1fc4e2c00c9b305093e04
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311317
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12944
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Rizwan Qureshi 2015-11-20 11:46:54 +05:30 committed by Patrick Georgi
parent b6319c1121
commit 2b1e8b3c3d
3 changed files with 256 additions and 1 deletions
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174
src/soc/intel/skylake/chip.c
View File

@ -347,6 +347,29 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
params->SkipMpInit = config->SkipMpInit; params->SkipMpInit = config->SkipMpInit;
for (i = 0; i < ARRAY_SIZE(config->domain_vr_config); i++) {
params->VrConfigEnable[i] =
config->domain_vr_config[i].vr_config_enable;
params->Psi1Threshold[i] =
config->domain_vr_config[i].psi1threshold;
params->Psi2Threshold[i] =
config->domain_vr_config[i].psi2threshold;
params->Psi3Threshold[i] =
config->domain_vr_config[i].psi3threshold;
params->Psi3Enable[i] =
config->domain_vr_config[i].psi3enable;
params->Psi4Enable[i] =
config->domain_vr_config[i].psi4enable;
params->ImonSlope[i] =
config->domain_vr_config[i].imon_slope;
params->ImonOffset[i] =
config->domain_vr_config[i].imon_offset;
params->IccMax[i] =
config->domain_vr_config[i].icc_max;
params->VrVoltageLimit[i] =
config->domain_vr_config[i].voltage_limit;
}
/* Show SPI controller if enabled in devicetree.cb */ /* Show SPI controller if enabled in devicetree.cb */
dev = dev_find_slot(0, PCH_DEVFN_SPI); dev = dev_find_slot(0, PCH_DEVFN_SPI);
params->ShowSpiController = dev->enabled; params->ShowSpiController = dev->enabled;
@ -762,7 +785,6 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
fsp_display_upd_value("TcoIrqEnable", 1, fsp_display_upd_value("TcoIrqEnable", 1,
original->TcoIrqEnable, original->TcoIrqEnable,
params->TcoIrqEnable); params->TcoIrqEnable);
fsp_display_upd_value("LockDownConfigGlobalSmi", 1, fsp_display_upd_value("LockDownConfigGlobalSmi", 1,
original->LockDownConfigGlobalSmi, original->LockDownConfigGlobalSmi,
params->LockDownConfigGlobalSmi); params->LockDownConfigGlobalSmi);
@ -827,6 +849,156 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original,
original->SerialIrqConfigStartFramePulse, original->SerialIrqConfigStartFramePulse,
params->SerialIrqConfigStartFramePulse); params->SerialIrqConfigStartFramePulse);
fsp_display_upd_value("Psi1Threshold[0]", 1,
original->Psi1Threshold[0],
params->Psi1Threshold[0]);
fsp_display_upd_value("Psi1Threshold[1]", 1,
original->Psi1Threshold[1],
params->Psi1Threshold[1]);
fsp_display_upd_value("Psi1Threshold[2]", 1,
original->Psi1Threshold[2],
params->Psi1Threshold[2]);
fsp_display_upd_value("Psi1Threshold[3]", 1,
original->Psi1Threshold[3],
params->Psi1Threshold[3]);
fsp_display_upd_value("Psi1Threshold[4]", 1,
original->Psi1Threshold[4],
params->Psi1Threshold[4]);
fsp_display_upd_value("Psi2Threshold[0]", 1,
original->Psi2Threshold[0],
params->Psi2Threshold[0]);
fsp_display_upd_value("Psi2Threshold[1]", 1,
original->Psi2Threshold[1],
params->Psi2Threshold[1]);
fsp_display_upd_value("Psi2Threshold[2]", 1,
original->Psi2Threshold[2],
params->Psi2Threshold[2]);
fsp_display_upd_value("Psi2Threshold[3]", 1,
original->Psi2Threshold[3],
params->Psi2Threshold[3]);
fsp_display_upd_value("Psi2Threshold[4]", 1,
original->Psi2Threshold[4],
params->Psi2Threshold[4]);
fsp_display_upd_value("Psi3Threshold[0]", 1,
original->Psi3Threshold[0],
params->Psi3Threshold[0]);
fsp_display_upd_value("Psi3Threshold[1]", 1,
original->Psi3Threshold[1],
params->Psi3Threshold[1]);
fsp_display_upd_value("Psi3Threshold[2]", 1,
original->Psi3Threshold[2],
params->Psi3Threshold[2]);
fsp_display_upd_value("Psi3Threshold[3]", 1,
original->Psi3Threshold[3],
params->Psi3Threshold[3]);
fsp_display_upd_value("Psi3Threshold[4]", 1,
original->Psi3Threshold[4],
params->Psi3Threshold[4]);
fsp_display_upd_value("Psi3Enable[0]", 1,
original->Psi3Enable[0],
params->Psi3Enable[0]);
fsp_display_upd_value("Psi3Enable[1]", 1,
original->Psi3Enable[1],
params->Psi3Enable[1]);
fsp_display_upd_value("Psi3Enable[2]", 1,
original->Psi3Enable[2],
params->Psi3Enable[2]);
fsp_display_upd_value("Psi3Enable[3]", 1,
original->Psi3Enable[3],
params->Psi3Enable[3]);
fsp_display_upd_value("Psi3Enable[4]", 1,
original->Psi3Enable[4],
params->Psi3Enable[4]);
fsp_display_upd_value("Psi4Enable[0]", 1,
original->Psi4Enable[0],
params->Psi4Enable[0]);
fsp_display_upd_value("Psi4Enable[1]", 1,
original->Psi4Enable[1],
params->Psi4Enable[1]);
fsp_display_upd_value("Psi4Enable[2]", 1,
original->Psi4Enable[2],
params->Psi4Enable[2]);
fsp_display_upd_value("Psi4Enable[3]", 1,
original->Psi4Enable[3],
params->Psi4Enable[3]);
fsp_display_upd_value("Psi4Enable[4]", 1,
original->Psi4Enable[4],
params->Psi4Enable[4]);
fsp_display_upd_value("ImonSlope[0]", 1,
original->ImonSlope[0],
params->ImonSlope[0]);
fsp_display_upd_value("ImonSlope[1]", 1,
original->ImonSlope[1],
params->ImonSlope[1]);
fsp_display_upd_value("ImonSlope[2]", 1,
original->ImonSlope[2],
params->ImonSlope[2]);
fsp_display_upd_value("ImonSlope[3]", 1,
original->ImonSlope[3],
params->ImonSlope[3]);
fsp_display_upd_value("ImonSlope[4]", 1,
original->ImonSlope[4],
params->ImonSlope[4]);
fsp_display_upd_value("ImonOffse[0]t", 1,
original->ImonOffset[0],
params->ImonOffset[0]);
fsp_display_upd_value("ImonOffse[1]t", 1,
original->ImonOffset[1],
params->ImonOffset[1]);
fsp_display_upd_value("ImonOffse[2]t", 1,
original->ImonOffset[2],
params->ImonOffset[2]);
fsp_display_upd_value("ImonOffse[3]t", 1,
original->ImonOffset[3],
params->ImonOffset[3]);
fsp_display_upd_value("ImonOffse[4]t", 1,
original->ImonOffset[4],
params->ImonOffset[4]);
fsp_display_upd_value("IccMax[0]", 1,
original->IccMax[0],
params->IccMax[0]);
fsp_display_upd_value("IccMax[1]", 1,
original->IccMax[1],
params->IccMax[1]);
fsp_display_upd_value("IccMax[2]", 1,
original->IccMax[2],
params->IccMax[2]);
fsp_display_upd_value("IccMax[3]", 1,
original->IccMax[3],
params->IccMax[3]);
fsp_display_upd_value("IccMax[4]", 1,
original->IccMax[4],
params->IccMax[4]);
fsp_display_upd_value("VrVoltageLimit[0]", 1,
original->VrVoltageLimit[0],
params->VrVoltageLimit[0]);
fsp_display_upd_value("VrVoltageLimit[1]", 1,
original->VrVoltageLimit[1],
params->VrVoltageLimit[1]);
fsp_display_upd_value("VrVoltageLimit[2]", 1,
original->VrVoltageLimit[2],
params->VrVoltageLimit[2]);
fsp_display_upd_value("VrVoltageLimit[3]", 1,
original->VrVoltageLimit[3],
params->VrVoltageLimit[3]);
fsp_display_upd_value("VrVoltageLimit[4]", 1,
original->VrVoltageLimit[4],
params->VrVoltageLimit[4]);
fsp_display_upd_value("VrConfigEnable[0]", 1,
original->VrConfigEnable[0],
params->VrConfigEnable[0]);
fsp_display_upd_value("VrConfigEnable[1]", 1,
original->VrConfigEnable[1],
params->VrConfigEnable[1]);
fsp_display_upd_value("VrConfigEnable[2]", 1,
original->VrConfigEnable[2],
params->VrConfigEnable[2]);
fsp_display_upd_value("VrConfigEnable[3]", 1,
original->VrConfigEnable[3],
params->VrConfigEnable[3]);
fsp_display_upd_value("VrConfigEnable[4]", 1,
original->VrConfigEnable[4],
params->VrConfigEnable[4]);
} }
static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device)

6
src/soc/intel/skylake/chip.h
View File

@ -25,6 +25,7 @@
#include <soc/pmc.h> #include <soc/pmc.h>
#include <soc/serialio.h> #include <soc/serialio.h>
#include <soc/usb.h> #include <soc/usb.h>
#include <soc/vr_config.h>
struct soc_intel_skylake_config { struct soc_intel_skylake_config {
/* /*
@ -325,6 +326,11 @@ struct soc_intel_skylake_config {
*/ */
u8 SerialIrqConfigStartFramePulse; u8 SerialIrqConfigStartFramePulse;
u8 SkipMpInit; u8 SkipMpInit;
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced
*/
struct vr_config domain_vr_config[NUM_VR_DOMAINS];
}; };
typedef struct soc_intel_skylake_config config_t; typedef struct soc_intel_skylake_config config_t;

77
src/soc/intel/skylake/include/soc/vr_config.h Normal file
View File

@ -0,0 +1,77 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc.
*/
/* VR Settings for each domain */
#ifndef _SOC_VR_CONFIG_H_
#define _SOC_VR_CONFIG_H_
struct vr_config {
/*
* The below settings will take effect when this is set to 1
* for that domain.
*/
int vr_config_enable;
/* Power State X current cuttof in 1/4 Amp increments
* Range is 0-128A
*/
int psi1threshold;
int psi2threshold;
int psi3threshold;
/* Enable power state 3/4 for different domains */
int psi3enable;
int psi4enable;
/*
* Imon slope correction. Specified in 1/100 increment
* values. Range is 0-200. 125 = 1.25
*/
int imon_slope;
/*
* Imon offset correction. Units 1/4, Range 0-255.
* Value of 100 = 100/4 = 25 offset.
*/
int imon_offset;
/* VR Icc Max limit. 0-255A in 1/4 A units. 400 = 100A */
int icc_max;
/* VR Voltage Limit. Range is 0-7999mV */
int voltage_limit;
};
/* VrConfig Settings for 5 domains
* 0 = System Agent, 1 = IA Core, 2 = Ring,
* 3 = GT unsliced, 4 = GT sliced
*/
enum vr_domain{
VR_SYSTEM_AGENT,
VR_IA_CORE,
VR_RING,
VR_GT_UNSLICED,
VR_GT_SLICED,
NUM_VR_DOMAINS
};
#endif