sb/intel/bd82x6x: Make the pch_enable_lpc hook optional

This also changes the name to mainboard_pch_lpc_setup to better
reflect that it is an optional mainboard hook.

This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.

Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/apple/macbookair4_2/romstage.c

@@ -20,7 +20,7 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <cbfs.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
 	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);

src/mainboard/asrock/b75pro3-m/romstage.c

@@ -23,10 +23,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/asus/h61m-cs/romstage.c

@@ -27,10 +27,6 @@
 #define SIO_DEV		PNP_DEV(SIO_PORT, 0)
 #define ACPI_DEV	PNP_DEV(SIO_PORT, NCT6779D_ACPI)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/asus/maximus_iv_gene-z/romstage.c

@@ -40,10 +40,6 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	static const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0);

src/mainboard/asus/p8h61-m_lx/romstage.c

@@ -41,7 +41,7 @@ const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 6 },
 };
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_or_config16(PCH_LPC_DEV, LPC_EN,
 			CNF1_LPC_EN | KBC_LPC_EN | LPT_LPC_EN | COMA_LPC_EN);

src/mainboard/asus/p8h61-m_pro/romstage.c

@@ -25,7 +25,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
 #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI)
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Enable the Super IO */
 	pci_write_config16(PCH_LPC_DEV, LPC_EN, CNF1_LPC_EN |

src/mainboard/asus/p8z77-m_pro/romstage.c

@@ -30,10 +30,6 @@
 #define GLOBAL_DEV PNP_DEV(0x2e, 0)
 #define SERIAL_DEV PNP_DEV(0x2e, NCT6779D_SP2)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	/* {enable, current, oc_pin} */
 	{ 1, 2, 0 }, /* Port 0: USB3 front internal header, top */

src/mainboard/compulab/intense_pc/romstage.c

@@ -22,7 +22,7 @@
 
 #define SIO_PORT 0x164e
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_devfn_t dev = PCH_LPC_DEV;
 

src/mainboard/gigabyte/ga-b75m-d3h/romstage.c

@@ -25,7 +25,7 @@
 #define SIO_GPIO PNP_DEV(SUPERIO_BASE, IT8728F_GPIO)
 #define SERIAL_DEV PNP_DEV(SUPERIO_BASE, 0x01)
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/gigabyte/ga-h61m-s2pv/romstage.c

@@ -23,10 +23,6 @@
 #define SUPERIO_GPIO PNP_DEV(0x2e, IT8728F_GPIO)
 #define SERIAL_DEV PNP_DEV(0x2e, 0x01)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/google/butterfly/romstage.c

@@ -28,7 +28,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #endif
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* EC Decode Range Port60/64 and Port62/66 */
 	/* Enable EC and PS/2 Keyboard/Mouse*/

src/mainboard/google/link/romstage.c

@@ -32,7 +32,7 @@
 
 #include <southbridge/intel/bd82x6x/chip.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Enable PS/2 Keyboard/Mouse, EC areas and COM1 */
 	pci_write_config16(PCH_LPC_DEV, LPC_EN, KBC_LPC_EN | MC_LPC_EN | \

src/mainboard/google/parrot/romstage.c

@@ -26,10 +26,6 @@
 #include <southbridge/intel/common/gpio.h>
 #include "ec/compal/ene932/ec.h"
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_late_rcba_config(void)
 {
 	u32 reg32;

src/mainboard/google/stout/romstage.c

@@ -30,7 +30,7 @@
 #include "ec.h"
 #include "onboard.h"
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/*
 	 * Enable:

src/mainboard/hp/2570p/romstage.c

@@ -20,10 +20,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/hp/kbc1126/ec.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 0, 1, 0 },

src/mainboard/hp/2760p/romstage.c

@@ -19,10 +19,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/hp/kbc1126/ec.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 1, 1, 0 },

src/mainboard/hp/8460p/romstage.c

@@ -23,10 +23,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* USB0, eSATA */
 	{ 1, 0, 0 }, /* USB charger */

src/mainboard/hp/8470p/romstage.c

@@ -22,10 +22,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 },
 	{ 1, 1, 0 },

src/mainboard/hp/8770w/romstage.c

@@ -23,10 +23,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, LPC47N217_SP1)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* Dock USB3.0 */
 	{ 1, 1, 0 }, /* Conn */

src/mainboard/hp/compaq_8200_elite_sff/romstage.c

@@ -27,10 +27,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 	{ 1, 0, -1 },

src/mainboard/hp/folio_9470m/romstage.c

@@ -21,10 +21,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/hp/kbc1126/ec.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1, 0 }, /* SSP1: dock */
 	{ 1, 1, 0 }, /* SSP2: left, EHCI Debug */

src/mainboard/hp/revolve_810_g1/romstage.c

@@ -24,10 +24,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <ec/hp/kbc1126/ec.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_late_rcba_config(void)
 {
 	RCBA32(BUC) = 0x00000000;

src/mainboard/hp/z220_sff_workstation/romstage.c

@@ -27,10 +27,6 @@
 
 #define SERIAL_DEV PNP_DEV(0x2e, NPCD378_SP2)
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, 0 },
 	{ 1, 0, 0 },

src/mainboard/intel/dcp847ske/early_southbridge.c

@@ -27,10 +27,6 @@
 #include "superio.h"
 #include "thermal.h"
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_late_rcba_config(void)
 {
 	/* Disable devices */

src/mainboard/intel/emeraldlake2/romstage.c

@@ -28,7 +28,7 @@
 
 #define SIO_PORT 0x164e
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_devfn_t dev = PCH_LPC_DEV;
 

src/mainboard/kontron/ktqm77/romstage.c

@@ -27,7 +27,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <superio/winbond/common/winbond.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Set COM3/COM1 decode ranges: 0x3e8/0x3f8 */
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0070);

src/mainboard/lenovo/l520/romstage.c

@@ -22,10 +22,6 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 0, -1 },
 	{ 1, 0, -1 },

src/mainboard/lenovo/s230u/romstage.c

@@ -27,7 +27,7 @@
 
 #define SPD_LEN 256
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 

src/mainboard/lenovo/t420/romstage.c

@@ -49,7 +49,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/lenovo/t420s/romstage.c

@@ -49,7 +49,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/lenovo/t430/romstage.c

@@ -49,10 +49,6 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
-{
-}
-
 /* FIXME: used T530 values here */
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{ 1, 1,  0 },

src/mainboard/lenovo/t430s/romstage.c

@@ -19,7 +19,7 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/lenovo/t520/romstage.c

@@ -51,7 +51,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/lenovo/t530/romstage.c

@@ -51,7 +51,7 @@ static void hybrid_graphics_init(void)
 	pci_write_config32(PCI_DEV(0, 0, 0), DEVEN, reg32);
 }
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/lenovo/x131e/romstage.c

@@ -20,10 +20,6 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 const struct southbridge_usb_port mainboard_usb_ports[] = {
 	{1, 1, 0},	/* P0: USB 3.0 1 (OC0) */
 	{1, 1, 0},	/* P1: USB 3.0 2 (OC0) */

src/mainboard/lenovo/x1_carbon_gen1/romstage.c

@@ -28,7 +28,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <cbfs.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/lenovo/x220/romstage.c

@@ -27,7 +27,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include <cpu/x86/msr.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/lenovo/x230/romstage.c

@@ -24,7 +24,7 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000);
 }

src/mainboard/msi/ms7707/romstage.c

@@ -20,7 +20,7 @@
 #include <southbridge/intel/common/pmbase.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	u16 reg16;
 	reg16 = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xa4);

src/mainboard/roda/rv11/variants/rv11/romstage.c

@@ -21,10 +21,6 @@
 #include <northbridge/intel/sandybridge/sandybridge.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 }

src/mainboard/roda/rv11/variants/rw11/romstage.c

@@ -25,10 +25,6 @@
 #include <superio/ite/it8783ef/it8783ef.h>
 #include <superio/ite/common/ite.h>
 
-void pch_enable_lpc(void)
-{
-}
-
 void mainboard_config_superio(void)
 {
 	const pnp_devfn_t dev = PNP_DEV(0x2e, IT8783EF_GPIO);

src/mainboard/samsung/lumpy/romstage.c

@@ -33,7 +33,7 @@
 #include <superio/smsc/lpc47n207/lpc47n207.h>
 #endif
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Set COM1/COM2 decode range */
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);

src/mainboard/samsung/stumpy/romstage.c

@@ -45,7 +45,7 @@
 #define SERIAL_DEV PNP_DEV(0x2e, IT8772F_SP1)
 #define GPIO_DEV PNP_DEV(0x2e, IT8772F_GPIO)
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	/* Set COM1/COM2 decode range */
 	pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x0010);

src/mainboard/sapphire/pureplatinumh61/romstage.c

@@ -21,7 +21,7 @@
 #include <northbridge/intel/sandybridge/raminit_native.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 
-void pch_enable_lpc(void)
+void mainboard_pch_lpc_setup(void)
 {
 	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000);
 }

src/northbridge/intel/sandybridge/sandybridge.h

@@ -212,7 +212,6 @@ void sandybridge_late_initialization(void);
 void northbridge_romstage_finalize(int s3resume);
 void early_init_dmi(void);
 
-void pch_enable_lpc(void);
 /* mainboard_early_init: Optional mainboard callback run after console init
    but before raminit. */
 void mainboard_early_init(int s3resume);

src/southbridge/intel/bd82x6x/early_pch.c

@@ -286,12 +286,16 @@ static void pch_enable_lpc_decode(void)
 	pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, config->gen4_dec);
 }
 
+__weak void mainboard_pch_lpc_setup(void)
+{
+}
+
 void early_pch_init(void)
 {
 
 	pch_enable_lpc_decode();
 
-	pch_enable_lpc();
+	mainboard_pch_lpc_setup();
 
 	pch_enable_bars();
 

src/southbridge/intel/bd82x6x/pch.h

@@ -75,6 +75,9 @@ void southbridge_rcba_config(void);
 /* Optional mainboard hook to do additional configuration
    on the RCBA config space. It is called after the raminit. */
 void mainboard_late_rcba_config(void);
+/* Optional mainboard hook to do additional LPC configuration
+   or to override what is set up by default. */
+void mainboard_pch_lpc_setup(void);
 void early_pch_init_native(void);
 void early_pch_init(void);
 void early_pch_init_native_dmi_pre(void);