security/intel/stm: Add options for STM build
This patch adds options that support building the STM as a part of the coreboot build. The option defaults assume that these configuration options are set as follows: IED_REGION_SIZE = 0x400000 SMM_RESERVED_SIZE = 0x200000 SMM_TSEG_SIZE = 0x800000 Original-Change-Id: I80ed7cbcb93468c5ff93d089d77742ce7b671a37 Original-Signed-off-by: Eugene Myers <cedarhouse@comcast.net> Original-Reviewed-on: https://review.coreboot.org/c/coreboot/+/44686 Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Original-Reviewed-by: ron minnich <rminnich@gmail.com> Change-Id: I982cde1299c87b5cf4f495905b53a6c107842956 Signed-off-by: Eugene Myers <edmyers@tycho.nsa.gov> Reviewed-on: https://review.coreboot.org/c/coreboot/+/55622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -29,20 +29,93 @@ menu "SMI Transfer Monitor (STM)"
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config MSEG_SIZE
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hex "mseg size"
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default 0x400000
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default 0x100000
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help
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STM only - 0x100000
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STM/PE - 0x300000+ depending on the amount of memory needed
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for the protected execution virtual
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machine (VM/PE)
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The MSEG_SIZE of 0x100000 assumes that:
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IED_REGION_SIZE = 0x400000
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SMM_RESERVED_SIZE = 0x200000
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SMM_TSEG_SIZE = 0x800000
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To use STM/PE, a larger MSEG_SIZE is necessary. This can be
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done by either increasing SMM_TSEG_SIZE or reducing the
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IED_REGION_SIZE and/or SMM_RESERVED_SIZE or some combination
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of the three.
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NOTE: The authors experience is that these configuration
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parameters have to be changed at the soc Konfig for them to
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be applied.
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Minimum sizes:
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STM only - 0x100000 - Supports up to 38 processor threads
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- 0x200000 - Supports up to 102 processor threads
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STM/PE - 0x300000+ depending on the amount of memory needed
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for the protected execution virtual
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machine (VM/PE)
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config STM_STMPE_ENABLED
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bool "STM/PE Enabled"
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default n
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help
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STM/PE provides for additional virtual machines in SMRAM
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that provides a protected execution environment for
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applications such as introspection, which need to be
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protected from malicious code. More information can be
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found on the stmpe branch of
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https://review.coreboot.org/STM
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config BIOS_RESOURCE_LIST_SIZE
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hex "bios_resource_list_size"
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hex "bios resource list size"
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default 0x1000
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help
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The BIOS resource list defines the resources that the
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SMI handler needs. This list is created during the
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coreboot bootup. Unless there has been a lot of elements
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added to this list, this value should not change.
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config STM_BINARY_FILE
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string "STM binary file"
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default "3rdparty/blobs/cpu/intel/stm/stm.bin"
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default "3rdparty/stm/Stm/build/StmPkg/Core/stm.bin"
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help
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Location of the STM binary file. The default location is
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where the file will be located when coreboot builds
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the STM.
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config STM_HEAPSIZE
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hex "stm heapsize"
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default 0x46000
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help
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The STM_HEAPSIZE defines the heap space that is available
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to the STM. The default size assumes a MSEG_SIZE of 0x100000.
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For STM/PE this size should be a minimum of 0x246000.
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config STM_TTYS0_BASE
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hex "stm uart"
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default TTYS0_BASE if TTYS0_BASE
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default 0x000
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help
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Defines the serial port for STM console output. 0x000 indicates
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no serial port.
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config STM_CBMEM_CONSOLE
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bool "STM cbmem console"
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default n
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depends on CONSOLE_CBMEM
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help
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Places the STM console output into the cbmem.
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choice
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prompt "Select STM console output"
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config STM_CONSOLE_DEBUG
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bool "Debug output"
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depends on STM_CBMEM_CONSOLE || STM_TTYS0_BASE
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help
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"Produces all STM console output"
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config STM_CONSOLE_RELEASE
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bool "Deactivate console output"
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help
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"No console output is produced"
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endchoice
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endmenu #STM
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@ -0,0 +1,33 @@
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# SPDX-License-Identifier: BSD-2-Clause
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project_name=STM
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project_dir=../../../../3rdparty/stm/
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build_dir=$(project_dir)/Stm/build
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project_git_branch=$(CONFIG_STM_GIT_BRANCH)
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ifeq ($(CONFIG_STM_CONSOLE_DEBUG),y)
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STM_BUILD="debug"
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endif
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ifeq ($(CONFIG_STM_CONSOLE_RELEASE),y)
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STM_BUILD="release"
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endif
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all: build
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build:
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echo "STM - Build"
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cd $(project_dir)/Stm; \
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mkdir -p build; \
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cd build; \
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cmake .. -DBIOS=coreboot \
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-DUART=$(CONFIG_STM_TTYS0_BASE) \
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-DHEAPSIZE=$(CONFIG_STM_HEAPSIZE) \
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-DCBMEM_ENABLE=$(CONFIG_STM_CBMEM_CONSOLE) \
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-DSTMPE_ENABLED=$(CONFIG_STM_STMPE_ENABLED) \
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-DBUILD=$(STM_BUILD); \
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$(MAKE);
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.PHONY: build
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@ -8,3 +8,13 @@ stm.bin-type := raw
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ramstage-$(CONFIG_STM) += SmmStm.c
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ramstage-$(CONFIG_STM) += StmPlatformSmm.c
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ramstage-$(CONFIG_STM) += StmPlatformResource.c
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3rdparty/stm/Stm/build/StmPkg/Core/stm.bin: $(obj)/config.h
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$(MAKE) -C src/security/intel/stm \
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CONFIG_STM_TTYSO_BASE=$(CONFIG_STM_TTYSO_BASE) \
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CONFIG_STM_HEAPSIZE=$(CONFIG_STM_HEAPSIZE) \
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CONFIG_STM_CONSOLE_DEBUG=$(CONFIG_STM_CONSOLE_DEBUG) \
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CONFIG_STM_CONSOLE_RELEASE=$(CONFIG_STM_CONSOLE_RELEASE) \
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CONFIG_STM_GIT_BRANCH=$(CONFIG_STM_GIT_BRANCH) \
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CONFIG_STM_STMPE_ENABLED=$(CONFIG_STM_STMPE_ENABLED) \
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CONFIG_STM_CBMEM_CONSOLE=$(CONFIG_STM_CBMEM_CONSOLE)
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