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mb/intel/tglrvp/variants/tglrvp_up4 - Enable onboard HDMI and type-C displays for TGL-Y RVP 

- Enable DDC pins for DDI-B
- Enable HPD pins for DDI-1/DDI-2
- Update MPHY/USB2 Mapping to match with the TGL-Y RVP schematic

BUG: System not able to detect displays attached to onboard micro-HDMI or Type-C connectors
TEST: hot-plug/unplug HDMI displays with onboard micro-HDMI connector and USB Type-C connectors to make sure the displays get detected and enabled

Change-Id: I08a1b16a8fa45cf0f366661395b9f2aa25c44935
Signed-off-by: Jason Le <jason.v.le@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Jason Le 2020-08-27 15:16:32 -07:00 committed by Tim Wawrzynczak
parent 411e7607d6
commit 2b3416134f
1 changed files with 14 additions and 4 deletions
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18
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
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@ -21,10 +21,13 @@ chip soc/intel/tigerlake
register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1 register "usb2_ports[0]" = "USB2_PORT_MID(OC3)" # Type-C Port1
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A port1 register "usb2_ports[2]" = "USB2_PORT_MID(OC0)" # M.2 Bluetooth, USB3/2 Type A Port1
register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A port1 register "usb2_ports[3]" = "USB2_PORT_MID(OC3)" # USB3/2 Type A Port 1
register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2 register "usb2_ports[4]" = "USB2_PORT_MID(OC3)" # Type-C Port2
register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-C Port3 / MECC
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Not used
register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Not used
register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Not used
register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT register "usb2_ports[9]" = "USB2_PORT_MID(OC3)" # CNVi/BT
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # USB3/2 Type A port1
@ -65,9 +68,16 @@ chip soc/intel/tigerlake
# enabling EDP in PortA # enabling EDP in PortA
register "DdiPortAConfig" = "1" register "DdiPortAConfig" = "1"
register "DdiPortAHpd" = "1"
register "DdiPortADdc" = "0"
register "DdiPortBHpd" = "1" register "DdiPortBHpd" = "1"
register "DdiPortBDdc" = "1"
register "DdiPortCHpd" = "0"
register "DdiPortCDdc" = "0"
register "DdiPort1Hpd" = "1" register "DdiPort1Hpd" = "1"
register "DdiPort1Ddc" = "1" register "DdiPort1Ddc" = "0"
register "DdiPort2Hpd" = "1"
register "DdiPort2Ddc" = "0"
register "SerialIoI2cMode" = "{ register "SerialIoI2cMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C0] = PchSerialIoPci,