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mb/intel/../../cml_u: Override LPSS related FSP UPD for CMLRVP 

This patch overrides required LPSS FSP UPDs for CMLRVP from devicetree.cb
File devicetree-override.cb will override required UPDs and is only
applicable to CML soc for now

Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2019-02-02 13:39:56 +05:30
parent 695f7249a4
commit 2b4ba5105c
1 changed files with 16 additions and 0 deletions
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16
src/mainboard/intel/coffeelake_rvp/variants/cml_u/devicetree.cb
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@ -8,6 +8,22 @@ chip soc/intel/cannonlake
register "SaGv" = "SaGv_Enabled"
register "ScsEmmcHs400Enabled" = "1"
register "HeciEnabled" = "1"
register "s0ix_enable" = "1"
register "SerialIoDevMode" = "{
[PchSerialIoIndexI2C0] = PchSerialIoPci,
[PchSerialIoIndexI2C1] = PchSerialIoPci,
[PchSerialIoIndexI2C2] = PchSerialIoPci,
[PchSerialIoIndexI2C3] = PchSerialIoPci,
[PchSerialIoIndexI2C4] = PchSerialIoDisabled,
[PchSerialIoIndexI2C5] = PchSerialIoPci,
[PchSerialIoIndexSPI0] = PchSerialIoPci,
[PchSerialIoIndexSPI1] = PchSerialIoPci,
[PchSerialIoIndexSPI2] = PchSerialIoDisabled,
[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
[PchSerialIoIndexUART1] = PchSerialIoDisabled,
[PchSerialIoIndexUART2] = PchSerialIoSkipInit,
}"
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC0)"
register "usb2_ports[1]" = "USB2_PORT_MID(OC0)"