mb/hp/280_g2/romstage.c: Correct CaVrefConfig setting

With DDR4, CA Vref goes to channel 0, and CH1 Vref goes to channel 1.

Change-Id: I64606824b4f82affb0fcfc78e68ba29859a1cc69
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/mainboard/hp/280_g2/romstage.c

@@ -23,8 +23,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 	get_spd_smbus(&blk);
 
+	mem_cfg->CaVrefConfig = 2;
 	mem_cfg->DqPinsInterleaved = true;
-
 	mem_cfg->UserBd = BOARD_TYPE_DESKTOP;
 
 	mem_cfg->MemorySpdDataLen = blk.len;