mediatek/mt8183: Add DDR driver of tx rx window perbit cal part

BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui, and inits DRAM successfully with related
     patches.

Change-Id: I4434897864993e254e1362416316470083351493
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/28842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>

src/soc/mediatek/mt8183/emi.c

@@ -131,7 +131,7 @@ static void set_rank_info_to_conf(const struct sdram_params *params)
 
 static void set_MRR_pinmux_mapping(void)
 {
-	for (u8 chn = 0; chn < CHANNEL_MAX; chn++) {
+	for (size_t chn = 0; chn < CHANNEL_MAX; chn++) {
 		const u8 *map = phy_mapping[chn];
 		write32(&ch[chn].ao.mrr_bit_mux1,
 			(map[0] << 0) | (map[1] << 8) |

src/soc/mediatek/mt8183/include/soc/dramc_pi_api.h

@@ -27,17 +27,11 @@
 #define dramc_dbg(_x_...)
 #endif
 
-#define ENABLE  1
-#define DISABLE 0
-
 #define DATLAT_TAP_NUMBER 32
 
-#define MAX_CMP_CPT_WAIT_LOOP 10000
-#define TIME_OUT_CNT 100
-
 #define DRAMC_BROADCAST_ON 0x1f
 #define DRAMC_BROADCAST_OFF 0x0
-#define MAX_BACKUP_REG_CNT 32
+#define TX_DQ_COARSE_TUNE_TO_FINE_TUNE_TAP 64
 
 #define IMP_LP4X_TERM_VREF_SEL		0x1b
 #define IMP_DRVP_LP4X_UNTERM_VREF_SEL	0x1a
@@ -49,11 +43,6 @@ enum dram_te_op {
 	TE_OP_READ_CHECK
 };
 
-enum {
-	DBI_OFF = 0,
-	DBI_ON
-};
-
 enum {
 	FSP_0 = 0,
 	FSP_1,
@@ -74,17 +63,6 @@ enum {
 	PASS_RANGE_NA = 0x7fff
 };
 
-enum {
-	GATING_OFF = 0,
-	GATING_ON = 1
-};
-
-enum {
-	CKE_FIXOFF = 0,
-	CKE_FIXON,
-	CKE_DYNAMIC
-};
-
 enum {
 	GATING_PATTERN_NUM = 0x23,
 	GATING_GOLDEND_DQSCNT = 0x4646

src/soc/mediatek/mt8183/include/soc/dramc_register.h

@@ -1145,7 +1145,7 @@ enum {
 };
 
 enum {
-	SHU1_BX_DQ7_R_DMDQMDBI_SHU_SHIFT = 7,
+	SHU1_BX_DQ7_R_DMDQMDBI_SHIFT = 7,
 	SHU1_BX_DQ7_R_DMRANKRXDVS_SHIFT = 0,
 	SHU1_BX_DQ7_R_DMRANKRXDVS_MASK = 0x0000000f,
 };

src/soc/mediatek/mt8183/include/soc/emi.h

@@ -33,6 +33,8 @@ struct sdram_params {
 	u16 delay_cell_unit;
 };
 
+extern const u8 phy_mapping[CHANNEL_MAX][16];
+
 int complex_mem_test(u8 *start, unsigned int len);
 size_t sdram_size(void);
 const struct sdram_params *get_sdram_config(void);

src/soc/mediatek/mt8183/include/soc/memlayout.ld

@@ -39,7 +39,7 @@ SECTIONS
 	SRAM_END(0x00120000)
 
 	SRAM_L2C_START(0x00200000)
-	OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 92K)
+	OVERLAP_DECOMPRESSOR_ROMSTAGE(0x000201000, 110K)
 	BOOTBLOCK(0x00227000, 89K)
 	VERSTAGE(0x0023E000, 114K)
 	SRAM_L2C_END(0x00280000)