mb/intel/adlrvp: do UART pad config at board-level

UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>

src/mainboard/intel/adlrvp/bootblock.c

@@ -3,7 +3,7 @@
 #include <baseboard/variants.h>
 #include <bootblock_common.h>
 
-void bootblock_mainboard_init(void)
+void bootblock_mainboard_early_init(void)
 {
 	variant_configure_early_gpio_pads();
 }

src/mainboard/intel/adlrvp/early_gpio.c

@@ -17,7 +17,17 @@ static const struct pad_config early_gpio_table[] = {
 	PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
 };
 
+static const struct pad_config early_uart_gpio_table[] = {
+	/* UART0 RX */
+	PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+	/* UART0 TX */
+	PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+};
+
 void variant_configure_early_gpio_pads(void)
 {
+	if (CONFIG(INTEL_LPSS_UART_FOR_CONSOLE))
+		gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table));
+
 	gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
 }