mb/intel/cannonlake_rvp/devicetree: Remove spurious CPP directives

The devicetree is not run through a C pre-processor, so remove it.

Change-Id: I161be45b2035f3a8724bf3217260e7571c429da8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27927
Reviewed-by: Naresh Solanki <naresh.solanki.2011@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2018-08-07 16:01:37 +02:00 committed by Nico Huber
parent c7b23e9dc8
commit 2b68cb08a8
1 changed files with 0 additions and 5 deletions

View File

@ -95,7 +95,6 @@ chip soc/intel/cannonlake
device pci 15.1 on end # I2C #1
device pci 15.2 off end # I2C #2
device pci 15.3 on
#if IS_ENABLED(CONFIG_INCLUDE_SND_MAX98373_NHLT)
chip drivers/i2c/max98373
register "vmon_slot_no" = "4"
register "imon_slot_no" = "5"
@ -112,7 +111,6 @@ chip soc/intel/cannonlake
register "name" = ""MAXL""
device i2c 32 on end
end
#elif IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)
chip drivers/i2c/da7219
register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20)"
register "btn_cfg" = "50"
@ -130,7 +128,6 @@ chip soc/intel/cannonlake
register "mic_amp_in_sel" = ""diff""
device i2c 1a on end
end
#endif
end # I2C #3
device pci 16.0 on end # Management Engine Interface 1
device pci 16.1 off end # Management Engine Interface 2
@ -167,7 +164,6 @@ chip soc/intel/cannonlake
end # LPC Interface
device pci 1f.1 on end # P2SB
device pci 1f.2 on end # Power Management Controller
#if IS_ENABLED(CONFIG_INCLUDE_SND_MAX98357_DA7219_NHLT)
device pci 1f.3 on
chip drivers/generic/max98357a
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)"
@ -175,7 +171,6 @@ chip soc/intel/cannonlake
device generic 0 on end
end
end # Intel HDA
#endif
device pci 1f.4 on end # SMBus
device pci 1f.5 on end # PCH SPI
device pci 1f.6 off end # GbE