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soc/intel/common: defines constant for C1E enable mask 

Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E
enable bit.  Define POWER_CTL_C1E_MASK to be used subsequently.

Change-Id: I7a5408f6678f56540929b7811764845b6dad1149
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27035
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Cole Nelson 2018-06-12 09:56:24 -07:00 committed by Patrick Georgi
parent c38960d7f3
commit 2b69b21c2d
1 changed files with 1 additions and 0 deletions
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1
src/soc/intel/common/block/include/intelblocks/msr.h
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@ -72,6 +72,7 @@
#define PRMRR_PHYS_MASK_LOCK (1 << 10)
#define PRMRR_PHYS_MASK_VALID (1 << 11)
#define MSR_POWER_CTL 0x1fc
#define POWER_CTL_C1E_MASK (1 << 1)
#define MSR_EVICT_CTL 0x2e0
#define MSR_SGX_OWNEREPOCH0 0x300
#define MSR_SGX_OWNEREPOCH1 0x301