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intel/strago: Fix for Crossystem "wpsw_cur" status 

The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East 
community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384] 
PINS [0 - 11]  and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26]
The discontinuity was not accounted for, hence the error.Original 
offset was 0x16 whereas it should be 0x13

TEST=Run crossystem and test wpsw_cur entry. If screw is present,
it should be 1 and if not present, it should be 0

Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c
Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291572
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com>
Reviewed-on: https://review.coreboot.org/13424
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kumar, Gomathi 2015-08-07 16:39:48 +05:30 committed by Martin Roth
parent d077b58c61
commit 2b9696239f
1 changed files with 2 additions and 2 deletions
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4
src/mainboard/intel/strago/acpi/chromeos.asl
View File

@ -23,11 +23,11 @@
*
* Note: We need to encode gpios within the 4 separate banks
* with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded
* as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
* as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
*/
Name(OIPG, Package() {
/* No physical recovery button */
Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
Package () { 0x0003, 1, 0x10016, "Braswell" },
Package () { 0x0003, 1, 0x10013, "Braswell" },
})