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AGESA f16kb: Enable MRC cache equivalent fastboot 

Try restoring previous memory training results from SPI flash
to improve raminit speed.

Change-Id: I6f4c2342e2eea6c1ecfb71da8564225b6230f51e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2017-03-26 11:56:43 +03:00
parent 8269096bd9
commit 2b9f5b5c12
1 changed files with 7 additions and 0 deletions
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7
src/northbridge/amd/agesa/family16kb/state_machine.c
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@ -30,6 +30,13 @@ void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early)
void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)
{ {
AGESA_STATUS status;
if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
status = OemInitResume(&Post->MemConfig.MemContext);
if (AGESA_SUCCESS == status)
Post->MemConfig.MemRestoreCtl = 1;
}
} }
void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post)