Cosmetics, whitespace and coding-style fixes for Intel CAR (trivial).
This is abuild-tested. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5901 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann
parent
d3f620299c
commit
2ba2b553b5
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@ -18,24 +18,24 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#include <cpu/x86/stack.h>
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#include <cpu/x86/mtrr.h>
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/* Save the BIST result */
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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/* Save the BIST result. */
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movl %eax, %ebp
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself */
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/* Send INIT IPI to all excluding ourself. */
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movl $0x000C4500, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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/* Zero out all Fixed Range and Variable Range MTRRs */
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/* Zero out all fixed range and variable range MTRRs. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) / 2), %edi
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xorl %eax, %eax
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@ -48,43 +48,43 @@ clear_mtrrs:
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dec %edi
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jnz clear_mtrrs
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/* Configure the default memory type to uncacheable */
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/* Configure the default memory type to uncacheable. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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/* Set cache as ram base address */
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/* Set Cache-as-RAM base address. */
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movl $(MTRRphysBase_MSR(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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/* Set cache as ram mask */
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/* Set Cache-as-RAM mask. */
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movl $(MTRRphysMask_MSR(0)), %ecx
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movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
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xorl %edx, %edx
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wrmsr
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/* Enable MTRR */
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/* Enable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $(1 << 11), %eax
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wrmsr
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/* Enable L2 Cache */
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/* Enable L2 cache. */
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movl $0x11e, %ecx
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rdmsr
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orl $(1 << 8), %eax
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wrmsr
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/* CR0.CD = 0, CR0.NW = 0 */
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~((1 << 30) | (1 << 29))), %eax
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invd
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movl %eax, %cr0
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/* Clear the cache memory reagion */
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/* Clear the cache memory reagion. */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE / 4), %ecx
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@ -92,7 +92,7 @@ clear_mtrrs:
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xorl %eax, %eax
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rep stosl
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/* Enable Cache As RAM mode by disabling cache */
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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@ -116,42 +116,42 @@ clear_mtrrs:
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wrmsr
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#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
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/* enable cache */
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~((1 << 30) | (1 << 29))), %eax
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movl %eax, %cr0
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/* Set up stack pointer */
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/* Set up the stack pointer. */
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#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
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/* leave some space for the struct ehci_debug_info */
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/* Leave some space for the struct ehci_debug_info. */
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movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
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#else
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movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
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#endif
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movl %eax, %esp
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/* Restore the BIST result */
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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post_code(0x23)
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/* Call romstage.c main function */
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/* Call romstage.c main function. */
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call main
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post_code(0x2f)
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post_code(0x30)
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/* Disable Cache */
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/* Disable cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x31)
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/* Disable MTRR */
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/* Disable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~(1 << 11)), %eax
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@ -175,21 +175,21 @@ clear_mtrrs:
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post_code(0x33)
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/* Enable Cache */
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/* Enable cache. */
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movl %cr0, %eax
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andl $~((1 << 30) | (1 << 29)), %eax
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movl %eax, %cr0
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post_code(0x36)
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/* Disable Cache */
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/* Disable cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x38)
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/* Enable Write Back and Speculative Reads for the first 1MB */
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/* Enable Write Back and Speculative Reads for the first 1MB. */
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movl $MTRRphysBase_MSR(0), %ecx
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movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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@ -201,14 +201,14 @@ clear_mtrrs:
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post_code(0x39)
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/* And Enable Cache again after setting MTRRs */
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/* And enable cache again after setting MTRRs. */
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movl %cr0, %eax
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andl $~((1 << 30) | (1 << 29)), %eax
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movl %eax, %cr0
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post_code(0x3a)
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/* Enable MTRR */
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/* Enable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $(1 << 11), %eax
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@ -216,16 +216,16 @@ clear_mtrrs:
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post_code(0x3b)
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/* Invalidate the cache again */
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/* Invalidate the cache again. */
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invd
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post_code(0x3c)
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/* clear boot_complete flag */
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/* Clear boot_complete flag. */
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xorl %ebp, %ebp
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__main:
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post_code(0x11)
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cld /* clear direction flag */
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cld /* Clear direction flag. */
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movl %ebp, %esi
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@ -18,24 +18,24 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#include <cpu/x86/stack.h>
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#include <cpu/x86/mtrr.h>
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/* Save the BIST result */
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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/* Save the BIST result. */
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movl %eax, %ebp
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself */
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/* Send INIT IPI to all excluding ourself. */
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movl $0x000C4500, %eax
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movl $0xFEE00300, %esi
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movl %eax, (%esi)
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/* Zero out all Fixed Range and Variable Range MTRRs */
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/* Zero out all fixed range and variable range MTRRs. */
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) / 2), %edi
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xorl %eax, %eax
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@ -48,43 +48,43 @@ clear_mtrrs:
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dec %edi
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jnz clear_mtrrs
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/* Configure the default memory type to uncacheable */
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/* Configure the default memory type to uncacheable. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~0x00000cff), %eax
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wrmsr
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/* Set cache as ram base address */
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/* Set Cache-as-RAM base address. */
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movl $(MTRRphysBase_MSR(0)), %ecx
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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/* Set cache as ram mask */
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/* Set Cache-as-RAM mask. */
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movl $(MTRRphysMask_MSR(0)), %ecx
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movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
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movl $0x0000000f, %edx
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wrmsr
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/* Enable MTRR */
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/* Enable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $(1 << 11), %eax
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wrmsr
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/* Enable L2 Cache */
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/* Enable L2 cache. */
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movl $0x11e, %ecx
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rdmsr
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orl $(1 << 8), %eax
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wrmsr
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/* CR0.CD = 0, CR0.NW = 0 */
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/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
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movl %cr0, %eax
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andl $(~((1 << 30) | (1 << 29))), %eax
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invd
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movl %eax, %cr0
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/* Clear the cache memory reagion */
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/* Clear the cache memory reagion. */
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movl $CACHE_AS_RAM_BASE, %esi
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movl %esi, %edi
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movl $(CACHE_AS_RAM_SIZE / 4), %ecx
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@ -92,7 +92,7 @@ clear_mtrrs:
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xorl %eax, %eax
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rep stosl
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/* Enable Cache As RAM mode by disabling cache */
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/* Enable Cache-as-RAM mode by disabling cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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@ -116,42 +116,42 @@ clear_mtrrs:
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wrmsr
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#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
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/* enable cache */
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/* Enable cache. */
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movl %cr0, %eax
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andl $(~((1 << 30) | (1 << 29))), %eax
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movl %eax, %cr0
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/* Set up stack pointer */
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/* Set up the stack pointer. */
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#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
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/* leave some space for the struct ehci_debug_info */
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/* Leave some space for the struct ehci_debug_info. */
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movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
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#else
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movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
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#endif
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movl %eax, %esp
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/* Restore the BIST result */
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/* Restore the BIST result. */
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movl %ebp, %eax
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movl %esp, %ebp
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pushl %eax
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post_code(0x23)
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/* Call romstage.c main function */
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/* Call romstage.c main function. */
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call main
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post_code(0x2f)
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post_code(0x30)
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/* Disable Cache */
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/* Disable cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x31)
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/* Disable MTRR */
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/* Disable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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andl $(~(1 << 11)), %eax
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@ -175,22 +175,21 @@ clear_mtrrs:
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post_code(0x33)
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/* Enable Cache */
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/* Enable cache. */
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movl %cr0, %eax
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andl $~((1 << 30) | (1 << 29)), %eax
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movl %eax, %cr0
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post_code(0x36)
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/* Disable Cache */
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/* Disable cache. */
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movl %cr0, %eax
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orl $(1 << 30), %eax
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movl %eax, %cr0
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post_code(0x38)
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/* Enable Write Back and Speculative Reads for the first 1MB */
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/* Enable Write Back and Speculative Reads for the first 1MB. */
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movl $MTRRphysBase_MSR(0), %ecx
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movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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@ -202,14 +201,14 @@ clear_mtrrs:
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post_code(0x39)
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/* And Enable Cache again after setting MTRRs */
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/* And enable cache again after setting MTRRs. */
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movl %cr0, %eax
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andl $~((1 << 30) | (1 << 29)), %eax
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movl %eax, %cr0
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post_code(0x3a)
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/* Enable MTRR */
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/* Enable MTRR. */
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $(1 << 11), %eax
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@ -217,16 +216,16 @@ clear_mtrrs:
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post_code(0x3b)
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/* Invalidate the cache again */
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/* Invalidate the cache again. */
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invd
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post_code(0x3c)
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/* clear boot_complete flag */
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/* Clear boot_complete flag. */
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xorl %ebp, %ebp
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__main:
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post_code(0x11)
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cld /* clear direction flag */
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cld /* Clear direction flag. */
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movl %ebp, %esi
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@ -18,19 +18,19 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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#include <cpu/x86/stack.h>
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#include <cpu/x86/mtrr.h>
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/* Save the BIST result */
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#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
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#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
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/* Save the BIST result. */
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movl %eax, %ebp
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||||
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cache_as_ram:
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post_code(0x20)
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/* Send INIT IPI to all excluding ourself */
|
||||
/* Send INIT IPI to all excluding ourself. */
|
||||
movl $0x000C4500, %eax
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||||
movl $0xFEE00300, %esi
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||||
movl %eax, (%esi)
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|
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@ -42,7 +42,7 @@ cache_as_ram:
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orl $((1 << 5) | (1 << 7)), %edx
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wrmsr
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/* Zero out all Fixed Range and Variable Range MTRRs */
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/* Zero out all fixed range and variable range MTRRs. */
|
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movl $mtrr_table, %esi
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movl $((mtrr_table_end - mtrr_table) / 2), %edi
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xorl %eax, %eax
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@ -55,43 +55,43 @@ clear_mtrrs:
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dec %edi
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jnz clear_mtrrs
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/* Configure the default memory type to uncacheable */
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||||
/* Configure the default memory type to uncacheable. */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
rdmsr
|
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andl $(~0x00000cff), %eax
|
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wrmsr
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|
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/* Set cache as ram base address */
|
||||
/* Set Cache-as-RAM base address. */
|
||||
movl $(MTRRphysBase_MSR(0)), %ecx
|
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movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax
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xorl %edx, %edx
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wrmsr
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/* Set cache as ram mask */
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/* Set Cache-as-RAM mask. */
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movl $(MTRRphysMask_MSR(0)), %ecx
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movl $(~((CACHE_AS_RAM_SIZE - 1)) | (1 << 11)), %eax
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movl $0x0000000f, %edx
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wrmsr
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/* Enable MTRR */
|
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/* Enable MTRR. */
|
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movl $MTRRdefType_MSR, %ecx
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rdmsr
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orl $(1 << 11), %eax
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wrmsr
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/* Enable L2 Cache */
|
||||
/* Enable L2 cache. */
|
||||
movl $0x11e, %ecx
|
||||
rdmsr
|
||||
orl $(1 << 8), %eax
|
||||
wrmsr
|
||||
|
||||
/* CR0.CD = 0, CR0.NW = 0 */
|
||||
/* Enable cache (CR0.CD = 0, CR0.NW = 0). */
|
||||
movl %cr0, %eax
|
||||
andl $(~((1 << 30) | (1 << 29))), %eax
|
||||
invd
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Clear the cache memory reagion */
|
||||
/* Clear the cache memory reagion. */
|
||||
movl $CACHE_AS_RAM_BASE, %esi
|
||||
movl %esi, %edi
|
||||
movl $(CACHE_AS_RAM_SIZE / 4), %ecx
|
||||
|
|
@ -99,7 +99,7 @@ clear_mtrrs:
|
|||
xorl %eax, %eax
|
||||
rep stosl
|
||||
|
||||
/* Enable Cache As RAM mode by disabling cache */
|
||||
/* Enable Cache-as-RAM mode by disabling cache. */
|
||||
movl %cr0, %eax
|
||||
orl $(1 << 30), %eax
|
||||
movl %eax, %cr0
|
||||
|
|
@ -123,42 +123,42 @@ clear_mtrrs:
|
|||
wrmsr
|
||||
#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
|
||||
|
||||
/* enable cache */
|
||||
/* Enable cache. */
|
||||
movl %cr0, %eax
|
||||
andl $(~((1 << 30) | (1 << 29))), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
/* Set up stack pointer */
|
||||
/* Set up the stack pointer. */
|
||||
#if defined(CONFIG_USBDEBUG) && (CONFIG_USBDEBUG == 1)
|
||||
/* leave some space for the struct ehci_debug_info */
|
||||
/* Leave some space for the struct ehci_debug_info. */
|
||||
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
|
||||
#else
|
||||
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
|
||||
#endif
|
||||
movl %eax, %esp
|
||||
|
||||
/* Restore the BIST result */
|
||||
/* Restore the BIST result. */
|
||||
movl %ebp, %eax
|
||||
movl %esp, %ebp
|
||||
pushl %eax
|
||||
|
||||
post_code(0x23)
|
||||
|
||||
/* Call romstage.c main function */
|
||||
/* Call romstage.c main function. */
|
||||
call main
|
||||
|
||||
post_code(0x2f)
|
||||
|
||||
post_code(0x30)
|
||||
|
||||
/* Disable Cache */
|
||||
/* Disable cache. */
|
||||
movl %cr0, %eax
|
||||
orl $(1 << 30), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
post_code(0x31)
|
||||
|
||||
/* Disable MTRR */
|
||||
/* Disable MTRR. */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
rdmsr
|
||||
andl $(~(1 << 11)), %eax
|
||||
|
|
@ -182,21 +182,21 @@ clear_mtrrs:
|
|||
|
||||
post_code(0x33)
|
||||
|
||||
/* Enable Cache */
|
||||
/* Enable cache. */
|
||||
movl %cr0, %eax
|
||||
andl $~((1 << 30) | (1 << 29)), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
post_code(0x36)
|
||||
|
||||
/* Disable Cache */
|
||||
/* Disable cache. */
|
||||
movl %cr0, %eax
|
||||
orl $(1 << 30), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
post_code(0x38)
|
||||
|
||||
/* Enable Write Back and Speculative Reads for the first 1MB */
|
||||
/* Enable Write Back and Speculative Reads for the first 1MB. */
|
||||
movl $MTRRphysBase_MSR(0), %ecx
|
||||
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
|
||||
xorl %edx, %edx
|
||||
|
|
@ -208,14 +208,14 @@ clear_mtrrs:
|
|||
|
||||
post_code(0x39)
|
||||
|
||||
/* And Enable Cache again after setting MTRRs */
|
||||
/* And enable cache again after setting MTRRs. */
|
||||
movl %cr0, %eax
|
||||
andl $~((1 << 30) | (1 << 29)), %eax
|
||||
movl %eax, %cr0
|
||||
|
||||
post_code(0x3a)
|
||||
|
||||
/* Enable MTRR */
|
||||
/* Enable MTRR. */
|
||||
movl $MTRRdefType_MSR, %ecx
|
||||
rdmsr
|
||||
orl $(1 << 11), %eax
|
||||
|
|
@ -230,16 +230,16 @@ clear_mtrrs:
|
|||
andl $~((1 << 5) | (1 << 7)), %edx
|
||||
wrmsr
|
||||
|
||||
/* Invalidate the cache again */
|
||||
/* Invalidate the cache again. */
|
||||
invd
|
||||
|
||||
post_code(0x3c)
|
||||
|
||||
/* clear boot_complete flag */
|
||||
/* Clear boot_complete flag. */
|
||||
xorl %ebp, %ebp
|
||||
__main:
|
||||
post_code(0x11)
|
||||
cld /* clear direction flag */
|
||||
cld /* Clear direction flag. */
|
||||
|
||||
movl %ebp, %esi
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue