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soc/intel/gpio: Add new macro for GPP PAD reset type as `Global Reset` 

This patch introduces a new macro for GPP PAD reset type as
`Global Reset` as documented in Alder Lake EDS doc 630603.

BUG=b:213293047
TEST=Able to build Google/Kano with this change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I39428911babc393dd10750801522a00d0b26d3e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-07-26 12:48:39 +00:00
parent 4a12f54654
commit 2ba4bfef7e
1 changed files with 5 additions and 0 deletions
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5
src/soc/intel/common/block/include/intelblocks/gpio_defs.h
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@ -45,6 +45,11 @@
#define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30) #define PAD_CFG0_LOGICAL_RESET_DEEP (1U << 30)
#define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30) #define PAD_CFG0_LOGICAL_RESET_PLTRST (2U << 30)
#define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30) #define PAD_CFG0_LOGICAL_RESET_RSMRST (3U << 30)
/*
* Alder Lake PCH onwards a newer bit field has added
* for GPP as `Global Reset`
*/
#define PAD_CFG0_LOGICAL_RESET_GLBRST (3U << 30)
/* /*
* Use the fourth bit in IntSel field to indicate gpio * Use the fourth bit in IntSel field to indicate gpio