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intel car: Remove references to DCACHE_RAM_ROMSTACK_SIZE 

Not referenced in code.

Change-Id: Iea91f4418eb122fb647ec0f4f42cb786e8eadf23
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17268
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Kyösti Mälkki 2016-07-26 14:03:31 +03:00
parent 76679d1e96
commit 2bad1e7f49
3 changed files with 6 additions and 27 deletions
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13
src/soc/intel/baytrail/Kconfig
View File

@ -99,9 +99,9 @@ endif # HAVE_MRC
# | MRC usage |
# | |
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
# | Stack |\
# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
# | v |/
# | Stack |
# | | |
# | v |
# +-------------+
# | ^ |
# | | |
@ -131,13 +131,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
help
The amount of cache-as-ram region required by the reference code.
config DCACHE_RAM_ROMSTAGE_STACK_SIZE
hex
default 0x800
help
The amount of anticipated stack usage from the data cache
during pre-RAM ROM stage execution.
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n

13
src/soc/intel/braswell/Kconfig
View File

@ -75,9 +75,9 @@ config SMM_RESERVED_SIZE
# Cache As RAM region layout:
#
# +-------------+ DCACHE_RAM_BASE + DCACHE_RAM_SIZE
# | Stack |\
# | | | * DCACHE_RAM_ROMSTAGE_STACK_SIZE
# | v |/
# | Stack |
# | | |
# | v |
# +-------------+
# | ^ |
# | | |
@ -97,13 +97,6 @@ config DCACHE_RAM_SIZE
and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE
must add up to a power of 2.
config DCACHE_RAM_ROMSTAGE_STACK_SIZE
hex
default 0x800
help
The amount of anticipated stack usage from the data cache
during pre-ram ROM stage execution.
config RESET_ON_INVALID_RAMSTAGE_CACHE
bool "Reset the system on S3 wake when ramstage cache invalid."
default n

7
src/soc/intel/broadwell/Kconfig
View File

@ -106,13 +106,6 @@ config DCACHE_RAM_MRC_VAR_SIZE
help
The amount of cache-as-ram region required by the reference code.
config DCACHE_RAM_ROMSTAGE_STACK_SIZE
hex
default 0x2000
help
The amount of anticipated stack usage from the data cache
during pre-ram ROM stage execution.
config HAVE_MRC
bool "Add a Memory Reference Code binary"
help