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mainboard/google/zoombini/variants/meowth: fix gpio settings 

-change GPP_C12 (H1 IRQ) to use GPI_SCI_LOW and level triggered
-set gspi gpios to no connects if CONFIG_ZOOMBINI_USE_SPI_TPM not set

BUG=b:69011806
BRANCH=chromeos-2016.05
TEST='emerge-meowth coreboot' succeeds

Change-Id: Ida1d1050db12982c3c497656162cc84c62a77f70
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Nick Vaccaro 2017-12-20 16:48:17 -08:00 committed by Stefan Reinauer
parent 8508f7d182
commit 2baf49fa67
1 changed files with 8 additions and 4 deletions
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12
src/mainboard/google/zoombini/variants/meowth/gpio.c
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@ -98,8 +98,8 @@ static const struct pad_config gpio_table[] = {
NF1), /* UART_PCH_TX_DEBUG_RX */ NF1), /* UART_PCH_TX_DEBUG_RX */
/* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 0, DEEP), /* PP3300_TOUCH_EN */ /* UART0_RTS# */ PAD_CFG_GPO(GPP_C10, 0, DEEP), /* PP3300_TOUCH_EN */
/* UART0_CTS# */ PAD_NC(GPP_C11, NONE), /* UART0_CTS# */ PAD_NC(GPP_C11, NONE),
/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE, /* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
INVERT), /* H1_PCH_INT_ODL */ LEVEL), /* H1_PCH_INT_ODL */
/* UART1_TXD */ PAD_NC(GPP_C13, NONE), /* UART1_TXD */ PAD_NC(GPP_C13, NONE),
/* UART1_RTS# */ PAD_CFG_GPI_SCI(GPP_C14, NONE, DEEP, EDGE_SINGLE, /* UART1_RTS# */ PAD_CFG_GPI_SCI(GPP_C14, NONE, DEEP, EDGE_SINGLE,
NONE), /* TOUCHSCREEN_INT_ODL */ NONE), /* TOUCHSCREEN_INT_ODL */
@ -265,9 +265,13 @@ static const struct pad_config early_gpio_table[] = {
NF1), /* PCH_SPI_H1_3V3_MISO */ NF1), /* PCH_SPI_H1_3V3_MISO */
/* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP, /* GSPI0_MOSI */ PAD_CFG_NF(GPP_B18, NONE, DEEP,
NF1), /* PCH_SPI_H1_3V3_MOSI */ NF1), /* PCH_SPI_H1_3V3_MOSI */
#else
/* GSPI0_CS# */ PAD_NC(GPP_B15, NONE),
/* GSPI0_CLK */ PAD_NC(GPP_B16, NONE),
/* GSPI0_MISO */ PAD_NC(GPP_B17, NONE),
/* GSPI0_MOSI */ PAD_NC(GPP_B18, NONE),
#endif #endif
/* UART1_RXD */ PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_SINGLE, /* UART1_RXD */ PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP, LEVEL),
INVERT), /* H1_PCH_INT_ODL */
}; };
const struct pad_config *variant_gpio_table(size_t *num) const struct pad_config *variant_gpio_table(size_t *num)