adding preliminary, and almost certainly wrong, rumba support.
This is just a skeleton, basically, and will most likely not even compile yet. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2164 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
05c743a5eb
commit
2bb216a880
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@ -0,0 +1,6 @@
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dir /cpu/x86/tsc
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dir /cpu/x86/fpu
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dir /cpu/x86/mmx
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dir /cpu/x86/lapic
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dir /cpu/x86/cache
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driver model_gx2_init.o
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@ -0,0 +1,70 @@
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/*
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freebios/src/northbridge/nsc/gx1/cpu_setup.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Initialize the GX1 CPU configuration registers
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*/
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/* copied for gx2 for ron minnich, as a placeholder */
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/* USES: esi, ecx, eax */
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#include <cpu/amd/gx2def.h>
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movl %eax, %ebp /* preserve bist */
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cpu_setup_start:
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leal cpu_setup_table, %esi
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movl $cpu_setup_len, %ecx
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cpu_setup_loop:
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movw (%esi), %ax
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addl $2, %esi
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outb %al, $0x22
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movb %ah, %al
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outb %al, $0x23
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loop cpu_setup_loop
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movb $0xff, %al /* DIR1 -- Identification Register 1 */
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outb %al, $0x22
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inb $0x23, %al
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cmpb $0x63, %al /* Revision for GXLV rev 3 */
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jbe cpu_no_ccr4
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movb $0xe8, %al /* CCR4 */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x20, %al /* Enable FPU Fast Mode */
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outb %al, $0x23
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movb $0xf0, %al /* PCR1 --- Performace Control */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x02, %al /* Incrementor on, whatever that is */
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outb %al, $0x23
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movb $0x20, %al /* PCR0 --- Performace Control */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x20, %al /* Must be 1 according to data book */
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orb $0x04, %al /* Incrementor Margin 10 */
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outb %al, $0x23
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cpu_no_ccr4:
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jmp cpu_setup_end
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cpu_setup_table:
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.byte 0xc1, 0x00 /* NO SMIs */
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.byte 0xc3, 0x14 /* Enable CPU config register */
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.byte 0x20, 0x00
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.byte 0xb8, GX_BASE>>30 /* Enable GXBASE address */
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.byte 0xc2, 0x00
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.byte 0xe8, 0x98
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.byte 0xc3, 0xf8 /* Enable CPU config register */
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cpu_setup_len = (.-cpu_setup_table)/2
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cpu_setup_end:
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nop
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movl %ebp, %eax /* Restore bist */
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@ -0,0 +1,47 @@
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/*
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freebios/src/northbridge/nsc/gx2/gx_setup.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Setup the GX_BASE registers on a National Semiconductor Geode CPU
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*/
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#include <cpu/amd/gx2def.h>
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movl %eax, %ebp /* Preserve bist */
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gx_setup_start:
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leal gx_setup_table, %esi
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movl $gx_setup_len, %ecx
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movl $GX_BASE, %edi
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gx_setup_loop:
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movw (%esi), %di /* Only read the low word of address */
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addl $4, %esi
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movl (%esi), %eax /* Data */
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addl $4, %esi
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movl %eax, (%edi)
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loop gx_setup_loop
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jmp gx_setup_end
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gx_setup_table:
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/* Allow writes to config registers */
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.long DC_UNLOCK, DC_UNLOCK_MAGIC
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.long DC_GENERAL_CFG, 0
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.long DC_UNLOCK, 0
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.long BC_DRAM_TOP, 0x3fffffff
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.long BC_XMAP_1, 0x60
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.long BC_XMAP_2, 0
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.long BC_XMAP_3, 0
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.long MC_BANK_CFG, 0x00700070 /* No DIMMS installed */
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.long MC_MEM_CNTRL1, XBUSARB
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.long MC_GBASE_ADD, 0x7ff /* Almost 1GB */
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gx_setup_len = (.-gx_setup_table)/8
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gx_setup_end:
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nop
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movl %ebp, %eax /* Restore bist */
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <string.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#if 0
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#include <cpu/amd/gx2def.h>
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#include <arch/io.h>
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static void gx2_cpu_setup(void)
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{
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unsigned char rreg;
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unsigned char cpu_table[] = {
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0xc1, 0x00, /* NO SMIs */
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0xc3, 0x14, /* Enable CPU config register */
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0x20, 0x00, /* */
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0xb8, GX_BASE>>30, /* Enable GXBASE address */
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0xc2, 0x00,
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0xe8, 0x98,
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0xc3, 0xf8, /* Enable CPU config register */
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0x00, 0x00
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};
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unsigned char *cPtr = cpu_table;
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while(rreg = *cPtr++) {
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unsigned char rval = *cPtr++;
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outb(rreg, 0x22);
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outb(rval, 0x23);
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}
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outb(0xff, 0x22); /* DIR1 -- Identification register 1 */
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if(inb(0x23) > 0x63) { /* Rev greater than R3 */
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outb(0xe8, 0x22);
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outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */
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outb(0xf0, 0x22);
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outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */
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outb(0x20, 0x22);
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outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */
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/* Bit 2 Incrementor margin 10 */
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}
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}
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static void gx2_gx_setup(void)
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{
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unsigned long gx_setup_table[] = {
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GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC,
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GX_BASE + DC_GENERAL_CFG, 0,
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GX_BASE + DC_UNLOCK, 0,
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GX_BASE + BC_DRAM_TOP, 0x3fffffff,
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GX_BASE + BC_XMAP_1, 0x60,
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GX_BASE + BC_XMAP_2, 0,
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GX_BASE + BC_XMAP_3, 0,
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GX_BASE + MC_BANK_CFG, 0x00700070,
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GX_BASE + MC_MEM_CNTRL1, XBUSARB,
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GX_BASE + MC_GBASE_ADD, 0xff,
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0, 0
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};
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unsigned long *gxPtr = gx_setup_table;
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unsigned long *gxdPtr;
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unsigned long addr;
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while(addr = *gxPtr++) {
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gxdPtr = (unsigned long *)addr;
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*gxdPtr = *gxPtr++;
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}
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}
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#endif
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static void model_gx2_init(device_t dev)
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{
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#if 0
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gx2_cpu_setup();
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gx2_gx_setup();
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#endif
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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/* Enable the local cpu apics */
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setup_lapic();
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};
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static struct device_operations cpu_dev_ops = {
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.init = model_gx2_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_CYRIX, 0x0540 },
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{ 0, 0 },
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};
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static struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@ -0,0 +1,145 @@
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##
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## Compute the location and size of where this firmware image
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## (linuxBIOS plus bootloader) will live in the boot rom chip.
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##
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if USE_FALLBACK_IMAGE
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default ROM_SECTION_SIZE = FALLBACK_SIZE
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default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
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else
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default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
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default ROM_SECTION_OFFSET = 0
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end
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##
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## Compute the start location and size size of
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## The linuxBIOS bootloader.
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##
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default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
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default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
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##
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## Compute where this copy of linuxBIOS will start in the boot rom
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##
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default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
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##
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## Compute a range of ROM that can cached to speed up linuxBIOS,
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## execution speed.
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##
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## XIP_ROM_SIZE must be a power of 2.
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## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
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##
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default XIP_ROM_SIZE=65536
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default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
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##
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## Set all of the defaults for an x86 architecture
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##
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arch i386 end
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##
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## Build the objects we have code for in this directory.
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##
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driver mainboard.o
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if HAVE_PIRQ_TABLE object irq_tables.o end
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#object reset.o
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||||
##
|
||||
## Romcc output
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||||
##
|
||||
makerule ./failover.E
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
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end
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||||
|
||||
makerule ./failover.inc
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depends "$(MAINBOARD)/failover.c ./romcc"
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action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
|
||||
end
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||||
|
||||
makerule ./auto.E
|
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
|
||||
action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
|
||||
end
|
||||
makerule ./auto.inc
|
||||
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
|
||||
action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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||||
end
|
||||
|
||||
##
|
||||
## Build our 16 bit and 32 bit linuxBIOS entry code
|
||||
##
|
||||
mainboardinit cpu/x86/16bit/entry16.inc
|
||||
mainboardinit cpu/x86/32bit/entry32.inc
|
||||
ldscript /cpu/x86/16bit/entry16.lds
|
||||
ldscript /cpu/x86/32bit/entry32.lds
|
||||
|
||||
##
|
||||
## Build our reset vector (This is where linuxBIOS is entered)
|
||||
##
|
||||
if USE_FALLBACK_IMAGE
|
||||
mainboardinit cpu/x86/16bit/reset16.inc
|
||||
ldscript /cpu/x86/16bit/reset16.lds
|
||||
else
|
||||
mainboardinit cpu/x86/32bit/reset32.inc
|
||||
ldscript /cpu/x86/32bit/reset32.lds
|
||||
end
|
||||
|
||||
### Should this be in the northbridge code?
|
||||
mainboardinit arch/i386/lib/cpu_reset.inc
|
||||
|
||||
##
|
||||
## Include an id string (For safe flashing)
|
||||
##
|
||||
mainboardinit arch/i386/lib/id.inc
|
||||
ldscript /arch/i386/lib/id.lds
|
||||
|
||||
###
|
||||
### This is the early phase of linuxBIOS startup
|
||||
### Things are delicate and we test to see if we should
|
||||
### failover to another image.
|
||||
###
|
||||
if USE_FALLBACK_IMAGE
|
||||
ldscript /arch/i386/lib/failover.lds
|
||||
mainboardinit ./failover.inc
|
||||
end
|
||||
|
||||
###
|
||||
### O.k. We aren't just an intermediary anymore!
|
||||
###
|
||||
|
||||
##
|
||||
## Setup RAM
|
||||
##
|
||||
mainboardinit cpu/x86/fpu/enable_fpu.inc
|
||||
mainboardinit cpu/amd/model_gx1/cpu_setup.inc
|
||||
mainboardinit cpu/amd/model_gx1/gx_setup.inc
|
||||
mainboardinit ./auto.inc
|
||||
|
||||
##
|
||||
## Include the secondary Configuration files
|
||||
##
|
||||
dir /pc80
|
||||
config chip.h
|
||||
|
||||
chip northbridge/amd/gx2
|
||||
device pci_domain 0 on
|
||||
device pci 0.0 on end
|
||||
chip southbridge/amd/cs5535
|
||||
device pci 12.0 on
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 off end # Audio
|
||||
device pci 12.4 off end # VGA
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
chip cpu/amd/model_gx2
|
||||
end
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -0,0 +1,160 @@
|
|||
uses HAVE_MP_TABLE
|
||||
uses HAVE_PIRQ_TABLE
|
||||
uses USE_FALLBACK_IMAGE
|
||||
uses HAVE_FALLBACK_BOOT
|
||||
uses HAVE_HARD_RESET
|
||||
uses HAVE_OPTION_TABLE
|
||||
uses USE_OPTION_TABLE
|
||||
uses CONFIG_ROM_STREAM
|
||||
uses IRQ_SLOT_COUNT
|
||||
uses MAINBOARD
|
||||
uses MAINBOARD_VENDOR
|
||||
uses MAINBOARD_PART_NUMBER
|
||||
uses LINUXBIOS_EXTRA_VERSION
|
||||
uses ARCH
|
||||
uses FALLBACK_SIZE
|
||||
uses STACK_SIZE
|
||||
uses HEAP_SIZE
|
||||
uses ROM_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_IMAGE_SIZE
|
||||
uses ROM_SECTION_SIZE
|
||||
uses ROM_SECTION_OFFSET
|
||||
uses CONFIG_ROM_STREAM_START
|
||||
uses PAYLOAD_SIZE
|
||||
uses _ROMBASE
|
||||
uses _RAMBASE
|
||||
uses XIP_ROM_SIZE
|
||||
uses XIP_ROM_BASE
|
||||
uses HAVE_MP_TABLE
|
||||
uses CROSS_COMPILE
|
||||
uses CC
|
||||
uses HOSTCC
|
||||
uses OBJCOPY
|
||||
uses DEFAULT_CONSOLE_LOGLEVEL
|
||||
uses MAXIMUM_CONSOLE_LOGLEVEL
|
||||
uses CONFIG_CONSOLE_SERIAL8250
|
||||
uses TTYS0_BAUD
|
||||
uses TTYS0_BASE
|
||||
uses TTYS0_LCS
|
||||
uses CONFIG_UDELAY_TSC
|
||||
uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
|
||||
|
||||
## ROM_SIZE is the size of boot ROM that this board will use.
|
||||
default ROM_SIZE = 256*1024
|
||||
|
||||
###
|
||||
### Build options
|
||||
###
|
||||
|
||||
##
|
||||
## Build code for the fallback boot
|
||||
##
|
||||
default HAVE_FALLBACK_BOOT=1
|
||||
|
||||
##
|
||||
## no MP table
|
||||
##
|
||||
default HAVE_MP_TABLE=0
|
||||
|
||||
##
|
||||
## Build code to reset the motherboard from linuxBIOS
|
||||
##
|
||||
default HAVE_HARD_RESET=0
|
||||
|
||||
## Delay timer options
|
||||
##
|
||||
default CONFIG_UDELAY_TSC=1
|
||||
default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
|
||||
|
||||
##
|
||||
## Build code to export a programmable irq routing table
|
||||
##
|
||||
default HAVE_PIRQ_TABLE=1
|
||||
default IRQ_SLOT_COUNT=2
|
||||
#object irq_tables.o
|
||||
|
||||
##
|
||||
## Build code to export a CMOS option table
|
||||
##
|
||||
default HAVE_OPTION_TABLE=0
|
||||
|
||||
###
|
||||
### LinuxBIOS layout values
|
||||
###
|
||||
|
||||
## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
|
||||
default ROM_IMAGE_SIZE = 65536
|
||||
default FALLBACK_SIZE = 131072
|
||||
|
||||
##
|
||||
## Use a small 8K stack
|
||||
##
|
||||
default STACK_SIZE=0x2000
|
||||
|
||||
##
|
||||
## Use a small 16K heap
|
||||
##
|
||||
default HEAP_SIZE=0x4000
|
||||
|
||||
##
|
||||
## Only use the option table in a normal image
|
||||
##
|
||||
#default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
|
||||
default USE_OPTION_TABLE = 0
|
||||
|
||||
default _RAMBASE = 0x00004000
|
||||
|
||||
default CONFIG_ROM_STREAM = 1
|
||||
|
||||
##
|
||||
## The default compiler
|
||||
##
|
||||
default CROSS_COMPILE=""
|
||||
default CC="$(CROSS_COMPILE)gcc -m32"
|
||||
default HOSTCC="gcc"
|
||||
|
||||
##
|
||||
## The Serial Console
|
||||
##
|
||||
|
||||
# To Enable the Serial Console
|
||||
default CONFIG_CONSOLE_SERIAL8250=1
|
||||
|
||||
## Select the serial console baud rate
|
||||
default TTYS0_BAUD=115200
|
||||
#default TTYS0_BAUD=57600
|
||||
#default TTYS0_BAUD=38400
|
||||
#default TTYS0_BAUD=19200
|
||||
#default TTYS0_BAUD=9600
|
||||
#default TTYS0_BAUD=4800
|
||||
#default TTYS0_BAUD=2400
|
||||
#default TTYS0_BAUD=1200
|
||||
|
||||
# Select the serial console base port
|
||||
default TTYS0_BASE=0x3f8
|
||||
|
||||
# Select the serial protocol
|
||||
# This defaults to 8 data bits, 1 stop bit, and no parity
|
||||
default TTYS0_LCS=0x3
|
||||
|
||||
##
|
||||
### Select the linuxBIOS loglevel
|
||||
##
|
||||
## EMERG 1 system is unusable
|
||||
## ALERT 2 action must be taken immediately
|
||||
## CRIT 3 critical conditions
|
||||
## ERR 4 error conditions
|
||||
## WARNING 5 warning conditions
|
||||
## NOTICE 6 normal but significant condition
|
||||
## INFO 7 informational
|
||||
## DEBUG 8 debug-level messages
|
||||
## SPEW 9 Way too many details
|
||||
|
||||
## Request this level of debugging output
|
||||
default DEFAULT_CONSOLE_LOGLEVEL=8
|
||||
## At a maximum only compile in this level of debugging
|
||||
default MAXIMUM_CONSOLE_LOGLEVEL=8
|
||||
|
||||
end
|
||||
|
||||
|
|
@ -0,0 +1,55 @@
|
|||
#define ASSEMBLY 1
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <arch/romcc_io.h>
|
||||
#include <arch/hlt.h>
|
||||
#include "pc80/serial.c"
|
||||
#include "arch/i386/lib/console.c"
|
||||
#include "ram/ramtest.c"
|
||||
//#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
|
||||
//#include "superio/NSC/pc97317/pc97317_early_serial.c"
|
||||
//#include "northbridge/intel/i440bx/raminit.h"
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
|
||||
|
||||
//#include "debug.c"
|
||||
//#include "lib/delay.c"
|
||||
|
||||
#include "northbridge/amd/gx2/raminit.c"
|
||||
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
// pc97317_enable_serial(SERIAL_DEV, TTYS0_BASE);
|
||||
uart_init();
|
||||
console_init();
|
||||
|
||||
/* Halt if there was a built in self test failure */
|
||||
report_bist_failure(bist);
|
||||
|
||||
sdram_init();
|
||||
|
||||
/* Check all of memory */
|
||||
#if 0
|
||||
ram_check(0x00000000, msr.lo);
|
||||
#endif
|
||||
#if 0
|
||||
static const struct {
|
||||
unsigned long lo, hi;
|
||||
} check_addrs[] = {
|
||||
/* Check 16MB of memory @ 0*/
|
||||
{ 0x00000000, 0x01000000 },
|
||||
#if TOTAL_CPUS > 1
|
||||
/* Check 16MB of memory @ 2GB */
|
||||
{ 0x80000000, 0x81000000 },
|
||||
#endif
|
||||
};
|
||||
int i;
|
||||
for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
|
||||
ram_check(check_addrs[i].lo, check_addrs[i].hi);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
extern struct chip_operations mainboard_amd_rumba_ops;
|
||||
|
||||
struct mainboard_amd_rumba_config {
|
||||
int nothing;
|
||||
};
|
||||
|
|
@ -0,0 +1,74 @@
|
|||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
|
||||
static void print_debug_pci_dev(unsigned dev)
|
||||
{
|
||||
print_debug("PCI: ");
|
||||
print_debug_hex8((dev >> 16) & 0xff);
|
||||
print_debug_char(':');
|
||||
print_debug_hex8((dev >> 11) & 0x1f);
|
||||
print_debug_char('.');
|
||||
print_debug_hex8((dev >> 8) & 7);
|
||||
}
|
||||
|
||||
static void print_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_device(unsigned dev)
|
||||
{
|
||||
int i;
|
||||
print_debug_pci_dev(dev);
|
||||
print_debug("\r\n");
|
||||
|
||||
for(i = 0; i <= 255; i++) {
|
||||
unsigned char val;
|
||||
if ((i & 0x0f) == 0) {
|
||||
print_debug_hex8(i);
|
||||
print_debug_char(':');
|
||||
}
|
||||
val = pci_read_config8(dev, i);
|
||||
print_debug_char(' ');
|
||||
print_debug_hex8(val);
|
||||
if ((i & 0x0f) == 0x0f) {
|
||||
print_debug("\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void dump_pci_devices(void)
|
||||
{
|
||||
device_t dev;
|
||||
for(dev = PCI_DEV(0, 0, 0);
|
||||
dev <= PCI_DEV(0, 0x1f, 0x7);
|
||||
dev += PCI_DEV(0,0,1)) {
|
||||
uint32_t id;
|
||||
id = pci_read_config32(dev, PCI_VENDOR_ID);
|
||||
if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0xffff) ||
|
||||
(((id >> 16) & 0xffff) == 0x0000)) {
|
||||
continue;
|
||||
}
|
||||
dump_pci_device(dev);
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
#define ASSEMBLY 1
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <arch/io.h>
|
||||
#include "arch/romcc_io.h"
|
||||
#include "pc80/mc146818rtc_early.c"
|
||||
|
||||
static unsigned long main(unsigned long bist)
|
||||
{
|
||||
/* This is the primary cpu how should I boot? */
|
||||
if (do_normal_boot()) {
|
||||
goto normal_image;
|
||||
}
|
||||
else {
|
||||
goto fallback_image;
|
||||
}
|
||||
normal_image:
|
||||
asm volatile ("jmp __normal_image"
|
||||
: /* outputs */
|
||||
: "a" (bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
cpu_reset:
|
||||
asm volatile ("jmp __cpu_reset"
|
||||
: /* outputs */
|
||||
: "a"(bist) /* inputs */
|
||||
: /* clobbers */
|
||||
);
|
||||
fallback_image:
|
||||
return bist;
|
||||
}
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
||||
*
|
||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*2, /* there can be total 2 devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0x800, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x2, /* Device */
|
||||
0, /* Crap (miniport) */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
|
||||
}
|
||||
};
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr);
|
||||
}
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <arch/io.h>
|
||||
#include "chip.h"
|
||||
|
||||
struct chip_operations mainboard_amd_rumba_ops = {
|
||||
CHIP_NAME("AMD Rumba mainboard ")
|
||||
};
|
||||
|
||||
|
|
@ -0,0 +1,43 @@
|
|||
#if 0
|
||||
//#include "arch/romcc_io.h"
|
||||
#include <arch/io.h>
|
||||
|
||||
typedef unsigned device_t;
|
||||
|
||||
#define PCI_DEV(BUS, DEV, FN) ( \
|
||||
(((BUS) & 0xFF) << 16) | \
|
||||
(((DEV) & 0x1f) << 11) | \
|
||||
(((FN) & 0x7) << 8))
|
||||
|
||||
static void pci_write_config8(device_t dev, unsigned where, unsigned char value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outb(value, 0xCFC + (addr & 3));
|
||||
}
|
||||
|
||||
static void pci_write_config32(device_t dev, unsigned where, unsigned value)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
outl(value, 0xCFC);
|
||||
}
|
||||
|
||||
static unsigned pci_read_config32(device_t dev, unsigned where)
|
||||
{
|
||||
unsigned addr;
|
||||
addr = dev | where;
|
||||
outl(0x80000000 | (addr & ~3), 0xCF8);
|
||||
return inl(0xCFC);
|
||||
}
|
||||
|
||||
#include "../../../northbridge/amd/amdk8/reset_test.c"
|
||||
|
||||
void hard_reset(void)
|
||||
{
|
||||
set_bios_reset();
|
||||
pci_write_config8(PCI_DEV(1, 0x04, 0), 0x47, 1);
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
config chip.h
|
||||
object northbridge.o
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
struct northbridge_amd_gx2_config
|
||||
{
|
||||
};
|
||||
|
||||
extern struct chip_operations northbridge_amd_gx2_ops;
|
||||
|
|
@ -0,0 +1,213 @@
|
|||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <bitops.h>
|
||||
#include "chip.h"
|
||||
#include "northbridge.h"
|
||||
#include <cpu/amd/gx2def.h>
|
||||
|
||||
#define NORTHBRIDGE_FILE "northbridge.c"
|
||||
/*
|
||||
*/
|
||||
|
||||
static void optimize_xbus(device_t dev)
|
||||
{
|
||||
/* Optimise X-Bus performance */
|
||||
pci_write_config8(dev, 0x40, 0x1e);
|
||||
pci_write_config8(dev, 0x41, 0x52);
|
||||
pci_write_config8(dev, 0x43, 0xc1);
|
||||
pci_write_config8(dev, 0x44, 0x00);
|
||||
}
|
||||
|
||||
static void enable_shadow(device_t dev)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static void northbridge_init(device_t dev)
|
||||
{
|
||||
printk_debug("northbridge: %s()\n", __FUNCTION__);
|
||||
|
||||
optimize_xbus(dev);
|
||||
enable_shadow(dev);
|
||||
}
|
||||
|
||||
|
||||
static struct device_operations northbridge_operations = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = northbridge_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static struct pci_driver northbridge_driver __pci_driver = {
|
||||
.ops = &northbridge_operations,
|
||||
.vendor = PCI_VENDOR_ID_CYRIX,
|
||||
.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
|
||||
};
|
||||
|
||||
|
||||
|
||||
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
|
||||
|
||||
static void pci_domain_read_resources(device_t dev)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
printk_spew("%s:%s()\n", NORTHBRIDGE_FILE, __FUNCTION__);
|
||||
|
||||
/* Initialize the system wide io space constraints */
|
||||
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0,0));
|
||||
resource->limit = 0xffffUL;
|
||||
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
|
||||
/* Initialize the system wide memory resources constraints */
|
||||
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1,0));
|
||||
resource->limit = 0xffffffffULL;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
|
||||
}
|
||||
|
||||
static void ram_resource(device_t dev, unsigned long index,
|
||||
unsigned long basek, unsigned long sizek)
|
||||
{
|
||||
struct resource *resource;
|
||||
|
||||
if (!sizek) {
|
||||
return;
|
||||
}
|
||||
resource = new_resource(dev, index);
|
||||
resource->base = ((resource_t)basek) << 10;
|
||||
resource->size = ((resource_t)sizek) << 10;
|
||||
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
|
||||
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
|
||||
}
|
||||
|
||||
static void tolm_test(void *gp, struct device *dev, struct resource *new)
|
||||
{
|
||||
struct resource **best_p = gp;
|
||||
struct resource *best;
|
||||
best = *best_p;
|
||||
if (!best || (best->base > new->base)) {
|
||||
best = new;
|
||||
}
|
||||
*best_p = best;
|
||||
}
|
||||
|
||||
static uint32_t find_pci_tolm(struct bus *bus)
|
||||
{
|
||||
struct resource *min;
|
||||
uint32_t tolm;
|
||||
min = 0;
|
||||
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
|
||||
tolm = 0xffffffffUL;
|
||||
if (min && tolm > min->base) {
|
||||
tolm = min->base;
|
||||
}
|
||||
return tolm;
|
||||
}
|
||||
|
||||
#define FRAMEBUFFERK 4096
|
||||
|
||||
static void pci_domain_set_resources(device_t dev)
|
||||
{
|
||||
device_t mc_dev;
|
||||
uint32_t pci_tolm;
|
||||
|
||||
pci_tolm = find_pci_tolm(&dev->link[0]);
|
||||
mc_dev = dev->link[0].children;
|
||||
if (mc_dev) {
|
||||
unsigned int tomk, tolmk;
|
||||
unsigned int ramreg = 0;
|
||||
int i, idx;
|
||||
unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
|
||||
unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
|
||||
|
||||
for(i=0; i<0x20; i+= 0x10) {
|
||||
unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
|
||||
unsigned int mem_config = *mcreg;
|
||||
|
||||
if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
|
||||
continue;
|
||||
ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
|
||||
}
|
||||
|
||||
tomk = ramreg << 10;
|
||||
|
||||
/* Sort out the framebuffer size */
|
||||
tomk -= FRAMEBUFFERK;
|
||||
*bcdramtop = ((tomk << 10) - 1);
|
||||
*mcgbaseadd = (tomk >> 9);
|
||||
|
||||
printk_debug("BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
|
||||
printk_debug("MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
|
||||
|
||||
printk_debug("I would set ram size to %d Mbytes\n", (tomk >> 10));
|
||||
|
||||
/* Compute the top of Low memory */
|
||||
tolmk = pci_tolm >> 10;
|
||||
if (tolmk >= tomk) {
|
||||
/* The PCI hole does does not overlap the memory.
|
||||
*/
|
||||
tolmk = tomk;
|
||||
}
|
||||
/* Report the memory regions */
|
||||
idx = 10;
|
||||
ram_resource(dev, idx++, 0, tolmk);
|
||||
}
|
||||
assign_resources(&dev->link[0]);
|
||||
}
|
||||
|
||||
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
|
||||
{
|
||||
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
|
||||
return max;
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.enable_resources = enable_childrens_resources,
|
||||
.init = 0,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
};
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
initialize_cpus(&dev->link[0]);
|
||||
}
|
||||
|
||||
static void cpu_bus_noop(device_t dev)
|
||||
{
|
||||
}
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = cpu_bus_noop,
|
||||
.set_resources = cpu_bus_noop,
|
||||
.enable_resources = cpu_bus_noop,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
|
||||
dev->ops = &pci_domain_ops;
|
||||
pci_set_method(dev);
|
||||
}
|
||||
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
|
||||
dev->ops = &cpu_bus_ops;
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_amd_gx2_ops = {
|
||||
CHIP_NAME("AMD GX2 Northbridge")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
#ifndef NORTHBRIDGE_AMD_GX2_H
|
||||
#define NORTHBRIDGE_AMD_GX2_H
|
||||
|
||||
extern unsigned int gx2_scan_root_bus(device_t root, unsigned int max);
|
||||
|
||||
#endif /* NORTHBRIDGE_AMD_GX2_H */
|
||||
|
|
@ -0,0 +1,357 @@
|
|||
#include <cpu/amd/gx2def.h>
|
||||
|
||||
/*
|
||||
This software and ancillary information (herein called SOFTWARE )
|
||||
called LinuxBIOS is made available under the terms described
|
||||
here. The SOFTWARE has been approved for release with associated
|
||||
LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
|
||||
been authored by an employee or employees of the University of
|
||||
California, operator of the Los Alamos National Laboratory under
|
||||
Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
|
||||
U.S. Government has rights to use, reproduce, and distribute this
|
||||
SOFTWARE. The public may copy, distribute, prepare derivative works
|
||||
and publicly display this SOFTWARE without charge, provided that this
|
||||
Notice and any statement of authorship are reproduced on all copies.
|
||||
Neither the Government nor the University makes any warranty, express
|
||||
or implied, or assumes any liability or responsibility for the use of
|
||||
this SOFTWARE. If SOFTWARE is modified to produce derivative works,
|
||||
such modified SOFTWARE should be clearly marked, so as not to confuse
|
||||
it with the version available from LANL.
|
||||
*/
|
||||
/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
|
||||
* rminnich@lanl.gov
|
||||
*/
|
||||
|
||||
/* SDRAM initialization for GX1 - translated from Christer Weinigel's
|
||||
assembler version into C.
|
||||
|
||||
Hamish Guthrie 10/4/2005 hamish@prodigi.ch
|
||||
*/
|
||||
/* just converted to GX2 by ron minnich -- this is probably mostly wrong
|
||||
* I am just putting in a placeholder to start building gx2 support
|
||||
*/
|
||||
|
||||
#define NUM_REFRESH 8
|
||||
#define TEST_DATA1 0x05A5A5A5A
|
||||
#define TEST_DATA2 0x0DEADBEEF
|
||||
|
||||
void setGX2Mem(unsigned int addr, unsigned int data)
|
||||
{
|
||||
writel(data, (volatile void *)addr);
|
||||
}
|
||||
|
||||
unsigned int getGX2Mem(unsigned int addr)
|
||||
{
|
||||
return (unsigned int)readl((const volatile void *)addr);
|
||||
}
|
||||
|
||||
void do_refresh(void)
|
||||
{
|
||||
unsigned int tval, i;
|
||||
|
||||
outb(0x71, 0x80);
|
||||
tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL1);
|
||||
tval |= RFSHTST;
|
||||
for(i=0; i>NUM_REFRESH; i++)
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
outb(0x72, 0x80);
|
||||
}
|
||||
|
||||
|
||||
void enable_dimm(void)
|
||||
{
|
||||
unsigned int tval, i;
|
||||
|
||||
outb(0x73, 0x80);
|
||||
|
||||
/* start SDCLCK's */
|
||||
tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL1);
|
||||
tval &= ~SDCLKSTRT;
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
tval |= SDCLKSTRT;
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
|
||||
/* Unmask SDCLK's */
|
||||
tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL2);
|
||||
tval &= ~(SDCLK_MASK | SDCLKOUT_MASK);
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL2, tval);
|
||||
tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL2);
|
||||
|
||||
/* Wait for clocks to unmask */
|
||||
for(i=0; i<5000; i++)
|
||||
outb(0, 0xed);
|
||||
|
||||
/* Refresh memory */
|
||||
tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL1);
|
||||
tval |= RFSHTST;
|
||||
for(i=0; i<NUM_REFRESH; i++)
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
tval &= ~RFSHTST;
|
||||
|
||||
/* Start the SDCLK's */
|
||||
tval &= ~PROGRAM_SDRAM;
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
tval |= PROGRAM_SDRAM | 0x00002000; /* Set refresh timing */
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
tval &= ~PROGRAM_SDRAM;
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
|
||||
/* Refresh memory again */
|
||||
tval = getGX2Mem(GX_BASE + MC_MEM_CNTRL1);
|
||||
tval |= RFSHTST;
|
||||
for(i=0; i>NUM_REFRESH; i++)
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
|
||||
for(i=0; i<2000; i++)
|
||||
outb(0, 0xed);
|
||||
outb(0x74, 0x80);
|
||||
}
|
||||
|
||||
static unsigned int size_dimm(int dimm_shift)
|
||||
{
|
||||
int bank_cfg = 0x700; /* MC_BANK_CFG for 512M */
|
||||
unsigned int offset = 0x10000000; /* Offset 256M */
|
||||
int failed_flag = 1;
|
||||
|
||||
do {
|
||||
setGX2Mem(0, TEST_DATA1);
|
||||
setGX2Mem(offset, TEST_DATA2);
|
||||
setGX2Mem(0x100, 0); /* Clear the bus */
|
||||
if (getGX2Mem(0) != TEST_DATA1) {
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG,
|
||||
getGX2Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_SZ << dimm_shift));
|
||||
bank_cfg -= 0x100;
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG,
|
||||
getGX2Mem(GX_BASE + MC_BANK_CFG) | (bank_cfg << dimm_shift));
|
||||
do_refresh();
|
||||
offset >>= 1;
|
||||
} else {
|
||||
failed_flag = 0;
|
||||
break;
|
||||
}
|
||||
} while (bank_cfg >= 0);
|
||||
|
||||
if (failed_flag)
|
||||
return (0x0070 << dimm_shift);
|
||||
else
|
||||
return(getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_SZ << dimm_shift));
|
||||
|
||||
}
|
||||
|
||||
static unsigned int module_banks(int dimm_shift)
|
||||
{
|
||||
int page_size = 0x800; /* Smallest page = 1K * 2 banks */
|
||||
int comp_banks;
|
||||
|
||||
#if 0
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(getGX2Mem(GX_BASE + MC_BANK_CFG));
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
/* retrieve the page size from the MC register */
|
||||
page_size <<= (((getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
|
||||
|
||||
#if 0
|
||||
print_debug(" page_size = ");
|
||||
print_debug_hex32(page_size);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
comp_banks = (((getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12);
|
||||
page_size <<= comp_banks;
|
||||
|
||||
setGX2Mem(0, TEST_DATA1);
|
||||
setGX2Mem(page_size, TEST_DATA2);
|
||||
setGX2Mem(0x100, 0); /* Clear the bus */
|
||||
if (getGX2Mem(page_size) != TEST_DATA2) {
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG,
|
||||
getGX2Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_MOD_BNK << dimm_shift));
|
||||
do_refresh();
|
||||
}
|
||||
#if 0
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(getGX2Mem(GX_BASE + MC_BANK_CFG));
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
return(getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift));
|
||||
}
|
||||
|
||||
static unsigned int component_banks(int dimm_shift)
|
||||
{
|
||||
int page_size = 0x800; /* Smallest page = 1K * 2 banks */
|
||||
|
||||
#if 0
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(getGX2Mem(GX_BASE + MC_BANK_CFG));
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
page_size = page_size << (((getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
|
||||
|
||||
#if 0
|
||||
print_debug(" page_size = ");
|
||||
print_debug_hex32(page_size);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
|
||||
setGX2Mem(0, TEST_DATA1);
|
||||
setGX2Mem(page_size, TEST_DATA2);
|
||||
setGX2Mem(0x100, 0); /* Clear the bus */
|
||||
if (getGX2Mem(0) != TEST_DATA1) {
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG,
|
||||
getGX2Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_COMP_BNK << dimm_shift));
|
||||
do_refresh();
|
||||
}
|
||||
#if 0
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(getGX2Mem(GX_BASE + MC_BANK_CFG));
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
return(getGX2Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift));
|
||||
}
|
||||
|
||||
static unsigned int page_size(int dimm_shift)
|
||||
{
|
||||
unsigned int page_test_offset = 0x2000;
|
||||
unsigned int temp;
|
||||
int page_size_config = 0x40;
|
||||
unsigned int probe_config;
|
||||
|
||||
do {
|
||||
setGX2Mem(0, TEST_DATA1);
|
||||
setGX2Mem(page_test_offset, TEST_DATA2);
|
||||
setGX2Mem(0x100, 0);
|
||||
temp = getGX2Mem(0);
|
||||
setGX2Mem(0, 0);
|
||||
if(temp == TEST_DATA1) {
|
||||
#if 0
|
||||
print_debug(" Page size Config = ");
|
||||
print_debug_hex32(page_size_config << dimm_shift);
|
||||
print_debug("\r\n");
|
||||
#endif
|
||||
return(page_size_config << dimm_shift);
|
||||
}
|
||||
|
||||
temp = ~(DIMM_PG_SZ << dimm_shift);
|
||||
|
||||
probe_config = getGX2Mem(GX_BASE + MC_BANK_CFG);
|
||||
probe_config &= temp;
|
||||
|
||||
page_size_config -= 0x10;
|
||||
page_size_config <<= dimm_shift;
|
||||
|
||||
probe_config |= page_size_config;
|
||||
|
||||
page_size_config >>= dimm_shift;
|
||||
|
||||
page_test_offset >>= 1;
|
||||
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG, probe_config);
|
||||
do_refresh();
|
||||
} while (page_size_config >= 0);
|
||||
|
||||
return 0x70;
|
||||
}
|
||||
|
||||
static int dimm_detect(int dimm_shift)
|
||||
{
|
||||
unsigned int test;
|
||||
|
||||
print_debug("Probing for DIMM");
|
||||
print_debug_char((dimm_shift >> 4) + 0x30);
|
||||
print_debug("\r\n");
|
||||
|
||||
setGX2Mem(0, TEST_DATA1);
|
||||
setGX2Mem(0x100, 0);
|
||||
test = getGX2Mem(0);
|
||||
setGX2Mem(0, 0);
|
||||
|
||||
if (test != TEST_DATA1)
|
||||
return 0;
|
||||
|
||||
print_debug(" Found DIMM");
|
||||
print_debug_char((dimm_shift >> 4) + 0x30);
|
||||
print_debug("\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int size_memory(int dimm_shift, unsigned int mem_config)
|
||||
{
|
||||
|
||||
if (!dimm_detect(dimm_shift))
|
||||
return (mem_config);
|
||||
|
||||
mem_config &= (~(DIMM_PG_SZ << dimm_shift));
|
||||
mem_config |= (page_size(dimm_shift));
|
||||
|
||||
print_debug(" Page Size: ");
|
||||
print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4)));
|
||||
print_debug("\r\n");
|
||||
|
||||
/* Now do component banks detection */
|
||||
|
||||
mem_config &= (~(DIMM_COMP_BNK << dimm_shift));
|
||||
mem_config |= (component_banks(dimm_shift));
|
||||
|
||||
print_debug(" Component Banks: ");
|
||||
print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30);
|
||||
print_debug("\r\n");
|
||||
|
||||
/* Now do module banks */
|
||||
|
||||
mem_config &= (~(DIMM_MOD_BNK << dimm_shift));
|
||||
mem_config |= (module_banks(dimm_shift));
|
||||
|
||||
print_debug(" Module Banks: ");
|
||||
print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30);
|
||||
print_debug("\r\n");
|
||||
|
||||
mem_config &= (~(DIMM_SZ << dimm_shift));
|
||||
mem_config |= (size_dimm(dimm_shift));
|
||||
|
||||
print_debug(" DIMM size: ");
|
||||
print_debug_hex32(1 <<
|
||||
((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22);
|
||||
print_debug("\r\n");
|
||||
|
||||
return (mem_config);
|
||||
}
|
||||
|
||||
static void sdram_init(void)
|
||||
{
|
||||
unsigned int mem_config = 0x00700070;
|
||||
|
||||
print_debug("Setting up default parameters for memory\r\n");
|
||||
outb(0x70, 0x80);
|
||||
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
|
||||
setGX2Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG, 0x00700070); /* No DIMMS installed */
|
||||
setGX2Mem(GX_BASE + MC_SYNC_TIM1, 0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG, 0x57405740); /* Largest DIMM size
|
||||
0x4000 -- 2 module banks
|
||||
0x1000 -- 4 component banks
|
||||
0x0700 -- DIMM size 512MB
|
||||
0x0040 -- Page Size 16kB */
|
||||
|
||||
enable_dimm();
|
||||
|
||||
print_debug("Sizing memory\r\n");
|
||||
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG, 0x00705740);
|
||||
do_refresh();
|
||||
mem_config = size_memory(0, mem_config);
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG, 0x57400070);
|
||||
do_refresh();
|
||||
mem_config = size_memory(16, mem_config);
|
||||
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(mem_config);
|
||||
print_debug("\r\n");
|
||||
|
||||
setGX2Mem(GX_BASE + MC_BANK_CFG, mem_config);
|
||||
enable_dimm();
|
||||
outb(0x7e, 0x80);
|
||||
}
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 4
|
||||
struct mem_controller {
|
||||
device_t d0;
|
||||
uint16_t channel0[DIMM_SOCKETS];
|
||||
};
|
||||
|
||||
|
||||
#endif /* RAMINIT_H */
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#config chip.h
|
||||
driver cs5535.o
|
||||
#driver cs5535_pci.o
|
||||
driver cs5535_ide.o
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef _SOUTHBRIDGE_AMD_CS5535
|
||||
#define _SOUTHBRIDGE_AMD_CS5535
|
||||
|
||||
extern struct chip_operations southbridge_amd_cs5535_ops;
|
||||
|
||||
struct southbridge_amd_cs5535_config {
|
||||
/* PCI function enables so the pci scan bus finds the devices */
|
||||
int enable_ide;
|
||||
int enable_nvram;
|
||||
};
|
||||
|
||||
#endif /* _SOUTHBRIDGE_AMD_CS5535 */
|
||||
|
|
@ -0,0 +1,92 @@
|
|||
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <console/console.h>
|
||||
#include "cs5535.h"
|
||||
|
||||
static void nvram_on(struct device *dev)
|
||||
{
|
||||
#if 0
|
||||
volatile char *flash = (volatile unsigned char *)0xFFFc0000;
|
||||
unsigned char id1, id2;
|
||||
#endif
|
||||
unsigned char reg;
|
||||
|
||||
/* Enable writes to flash at top of memory */
|
||||
pci_write_config8(dev, 0x52, 0xee);
|
||||
|
||||
/* Set positive decode on ROM */
|
||||
/* Also, there is no apparent reason to turn off the devoce on the */
|
||||
/* IDE devices */
|
||||
|
||||
reg = pci_read_config8(dev, 0x5b);
|
||||
reg |= 1 << 5; /* ROM Decode */
|
||||
reg |= 1 << 3; /* Primary IDE decode */
|
||||
reg |= 1 << 4; /* Secondary IDE decode */
|
||||
|
||||
pci_write_config8(dev, 0x5b, reg);
|
||||
|
||||
#if 0 // just to test if the flash is accessible!
|
||||
*(flash + 0x555) = 0xaa;
|
||||
*(flash + 0x2aa) = 0x55;
|
||||
*(flash + 0x555) = 0x90;
|
||||
|
||||
id1 = *(volatile unsigned char *) flash;
|
||||
id2 = *(volatile unsigned char *) (flash + 1);
|
||||
|
||||
*flash = 0xf0;
|
||||
|
||||
printk_debug("Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
static void southbridge_init(struct device *dev)
|
||||
{
|
||||
printk_spew("cs5535: %s\n", __FUNCTION__);
|
||||
nvram_on(dev);
|
||||
}
|
||||
|
||||
/*
|
||||
static void dump_south(struct device *dev)
|
||||
{
|
||||
int i, j;
|
||||
|
||||
for(i=0; i<256; i+=16) {
|
||||
printk_debug("0x%02x: ", i);
|
||||
for(j=0; j<16; j++)
|
||||
printk_debug("%02x ", pci_read_config8(dev, i+j));
|
||||
printk_debug("\n");
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
static void southbridge_enable(struct device *dev)
|
||||
{
|
||||
printk_spew("%s: dev is %p\n", __FUNCTION__, dev);
|
||||
}
|
||||
|
||||
static void cs5535_pci_dev_enable_resources(device_t dev)
|
||||
{
|
||||
printk_spew("cs5535.c: %s()\n", __FUNCTION__);
|
||||
pci_dev_enable_resources(dev);
|
||||
enable_childrens_resources(dev);
|
||||
}
|
||||
|
||||
static struct device_operations southbridge_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = cs5535_pci_dev_enable_resources,
|
||||
.init = southbridge_init,
|
||||
.enable = southbridge_enable,
|
||||
.scan_bus = scan_static_bus,
|
||||
};
|
||||
|
||||
static struct pci_driver cs5535_pci_driver __pci_driver = {
|
||||
.ops = &southbridge_ops,
|
||||
.vendor = PCI_VENDOR_ID_CYRIX,
|
||||
.device = PCI_DEVICE_ID_CYRIX_5535_LEGACY,
|
||||
};
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
#ifndef _CS5535_H
|
||||
#define _CS5535_H
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include "cs5535.h"
|
||||
|
||||
static void ide_init(struct device *dev)
|
||||
{
|
||||
printk_spew("cs5535_ide: %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static void ide_enable(struct device *dev)
|
||||
{
|
||||
printk_spew("cs5535_ide: %s\n", __FUNCTION__);
|
||||
}
|
||||
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ide_init,
|
||||
.enable = ide_enable,
|
||||
};
|
||||
|
||||
static struct pci_driver ide_driver __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_AMD,
|
||||
.device = PCI_DEVICE_ID_AMD_5535_IDE,
|
||||
};
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
# Config file for the AMD rumba motherboard
|
||||
# This will make a target directory of rumba
|
||||
|
||||
target rumba
|
||||
mainboard amd/rumba
|
||||
|
||||
option ROM_SIZE=1024*256
|
||||
|
||||
romimage "normal"
|
||||
option USE_FALLBACK_IMAGE=0
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Normal"
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
# payload ../../../../../lnxieepro100.ebi
|
||||
# payload /etc/hosts
|
||||
payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
|
||||
end
|
||||
|
||||
romimage "fallback"
|
||||
option USE_FALLBACK_IMAGE=1
|
||||
option ROM_IMAGE_SIZE=0x10000
|
||||
option LINUXBIOS_EXTRA_VERSION=".0Fallback"
|
||||
# payload /usr/share/etherboot/5.1.9pre2-lnxi-lb/tg3--ide_disk.zelf
|
||||
# payload ../../../../tg3--ide_disk.zelf
|
||||
# payload ../../../../../lnxieepro100.ebia
|
||||
# payload /etc/hosts
|
||||
payload /home/hamish/work/etherboot/eb-5.2.6-lne100.elf
|
||||
end
|
||||
|
||||
buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
|
||||
|
|
@ -29,7 +29,8 @@ romimage "normal"
|
|||
# payload ../../../payloads/filo.zelf
|
||||
# payload ../../../payloads/tg3.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vga.zelf
|
||||
payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
|
||||
# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
|
||||
payload /tmp/filo.elf
|
||||
# payload ../../../payloads/forcedeth_vga.zelf
|
||||
# payload ../../../payloads/forcedeth--filo_hda2_vga_5_4.zelf
|
||||
# payload ../../../../../../elf/ram0_2.5_2.6.11.tiny.elf
|
||||
|
|
@ -58,7 +59,8 @@ romimage "fallback"
|
|||
# payload ../../../payloads/filo.zelf
|
||||
# payload ../../../payloads/tg3.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vga.zelf
|
||||
payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
|
||||
# payload ../../../../payloads/forcedeth--filo_hda2_vga.zelf
|
||||
payload /tmp/filo.elf
|
||||
# payload ../../../payloads/forcedeth_vga.zelf
|
||||
# payload ../../../payloads/tg3--filo_hda2_vga_5_4.zelf
|
||||
# payload ../../../payloads/tg3_vga.zelf
|
||||
|
|
|
|||
Loading…
Reference in New Issue