soc/amd/common: Move files to common/block
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and spi.c. The remaining files are AGESA related and will be part of a separate issue/commit. BUG=b:62240201 TEST=Build with no error gardenia and kahlee (no code change, just folder reorg). Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/22765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
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@ -17,7 +17,7 @@
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#include <device/device.h>
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#include <arch/acpi.h>
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#include <agesawrapper.h>
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#include <amd_pci_util.h>
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#include <amdblocks/amd_pci_util.h>
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/***********************************************************
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* These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.
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@ -23,7 +23,7 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <soc/southbridge.h>
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#include <amd_pci_util.h>
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#include <amdblocks/amd_pci_util.h>
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static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
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{
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@ -17,7 +17,7 @@
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#include <device/device.h>
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#include <arch/acpi.h>
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#include <agesawrapper.h>
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#include <amd_pci_util.h>
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#include <amdblocks/amd_pci_util.h>
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#include <cbmem.h>
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#include <baseboard/variants.h>
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#include <boardid.h>
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@ -23,7 +23,7 @@
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#include <arch/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <soc/southbridge.h>
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#include <amd_pci_util.h>
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#include <amdblocks/amd_pci_util.h>
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static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
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{
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@ -12,10 +12,9 @@ romstage-y += heapmanager.c
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ramstage-y += agesawrapper.c
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ramstage-y += amd_late_init.c
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ramstage-y += amd_pci_util.c
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ramstage-y += def_callouts.c
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ramstage-y += heapmanager.c
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ramstage-$(CONFIG_SPI_FLASH) += spi.c
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subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block
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endif
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@ -0,0 +1,6 @@
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config SOC_AMD_COMMON_BLOCK_PCI
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bool
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default n
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help
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This option builds functions used to program PCI interrupt
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routing, both PIC and APIC modes.
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@ -0,0 +1,5 @@
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)
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ramstage-y += amd_pci_util.c
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endif
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@ -18,7 +18,7 @@
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#include <device/pci.h>
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#include <arch/io.h>
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#include <string.h>
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#include <amd_pci_util.h>
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#include <amdblocks/amd_pci_util.h>
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#include <pc80/i8259.h>
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#include <soc/amd_pci_int_defs.h>
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@ -0,0 +1,5 @@
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config SOC_AMD_COMMON_BLOCK_S3
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bool
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default n
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help
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Select this option to add S3 related functions to the build.
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@ -0,0 +1,5 @@
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ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y)
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ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
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endif
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@ -46,8 +46,10 @@ config CPU_SPECIFIC_OPTIONS
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select SOC_AMD_PI
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select SOC_AMD_COMMON
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select SOC_AMD_COMMON_BLOCK
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select SOC_AMD_COMMON_BLOCK_PCI
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select SOC_AMD_COMMON_BLOCK_PSP
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select SOC_AMD_COMMON_BLOCK_CAR
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select SOC_AMD_COMMON_BLOCK_S3
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select C_ENVIRONMENT_BOOTBLOCK
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select BOOTBLOCK_CONSOLE
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select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH
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@ -24,7 +24,7 @@
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#include <device/pci_ids.h>
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#include <device/pci_ops.h>
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#include <cbmem.h>
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#include <amd_pci_util.h>
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#include <amdblocks/amd_pci_util.h>
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#include <soc/southbridge.h>
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#include <soc/smi.h>
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#include <soc/amd_pci_int_defs.h>
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