soc/amd/common: Move files to common/block

The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit.

BUG=b:62240201
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).

Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>

src/mainboard/amd/gardenia/mainboard.c

@@ -17,7 +17,7 @@
 #include <device/device.h>
 #include <arch/acpi.h>
 #include <agesawrapper.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 
 /***********************************************************
  * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01.

src/mainboard/amd/gardenia/mptable.c

@@ -23,7 +23,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <soc/southbridge.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 
 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
 {

src/mainboard/google/kahlee/mainboard.c

@@ -17,7 +17,7 @@
 #include <device/device.h>
 #include <arch/acpi.h>
 #include <agesawrapper.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 #include <cbmem.h>
 #include <baseboard/variants.h>
 #include <boardid.h>

src/mainboard/google/kahlee/mptable.c

@@ -23,7 +23,7 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <soc/southbridge.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 
 static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned int length)
 {

src/soc/amd/common/Makefile.inc

@@ -12,10 +12,9 @@ romstage-y += heapmanager.c
 
 ramstage-y += agesawrapper.c
 ramstage-y += amd_late_init.c
-ramstage-y += amd_pci_util.c
 ramstage-y += def_callouts.c
 ramstage-y += heapmanager.c
-ramstage-$(CONFIG_SPI_FLASH) += spi.c
+
 subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK) += block
 
 endif

src/soc/amd/common/block/pci/Kconfig

@@ -0,0 +1,6 @@
+config SOC_AMD_COMMON_BLOCK_PCI
+	bool
+	default n
+	help
+	  This option builds functions used to program PCI interrupt
+	  routing, both PIC and APIC modes.

src/soc/amd/common/block/pci/Makefile.inc

@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PCI),y)
+
+ramstage-y += amd_pci_util.c
+
+endif

src/soc/amd/common/block/pci/amd_pci_util.c

@@ -18,7 +18,7 @@
 #include <device/pci.h>
 #include <arch/io.h>
 #include <string.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 #include <pc80/i8259.h>
 #include <soc/amd_pci_int_defs.h>
 

src/soc/amd/common/block/s3/Kconfig

@@ -0,0 +1,5 @@
+config SOC_AMD_COMMON_BLOCK_S3
+	bool
+	default n
+	help
+	  Select this option to add S3 related functions to the build.

src/soc/amd/common/block/s3/Makefile.inc

@@ -0,0 +1,5 @@
+ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y)
+
+ramstage-$(CONFIG_HAVE_ACPI_RESUME) += spi.c
+
+endif

src/soc/amd/stoneyridge/Kconfig

@@ -46,8 +46,10 @@ config CPU_SPECIFIC_OPTIONS
 	select SOC_AMD_PI
 	select SOC_AMD_COMMON
 	select SOC_AMD_COMMON_BLOCK
+	select SOC_AMD_COMMON_BLOCK_PCI
 	select SOC_AMD_COMMON_BLOCK_PSP
 	select SOC_AMD_COMMON_BLOCK_CAR
+	select SOC_AMD_COMMON_BLOCK_S3
 	select C_ENVIRONMENT_BOOTBLOCK
 	select BOOTBLOCK_CONSOLE
 	select BOOT_DEVICE_SUPPORTS_WRITES if BOOT_DEVICE_SPI_FLASH

src/soc/amd/stoneyridge/southbridge.c

@@ -24,7 +24,7 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cbmem.h>
-#include <amd_pci_util.h>
+#include <amdblocks/amd_pci_util.h>
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 #include <soc/amd_pci_int_defs.h>