soc/intel/tigerlake: Drop redundant PcieRpEnable
The PcieRpEnable option is redundant to our on/off setting in the devicetrees. Let's use the common coreboot infrastructure instead. Thanks to Nicholas for doing all the mainboard legwork! Change-Id: Iacfef5f032278919f1fcf49e31fa42bcbf1eaf20 Signed-off-by: Nico Huber <nico.h@gmx.de> Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79920 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -154,7 +154,6 @@ chip soc/intel/tigerlake
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end
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end
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device ref pcie_rp3 on
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register "PcieRpEnable[2]" = "true"
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register "PcieRpLtrEnable[2]" = "true"
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register "PcieClkSrcUsage[1]" = "2"
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register "PcieClkSrcClkReq[1]" = "1"
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@ -167,14 +166,12 @@ chip soc/intel/tigerlake
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device ref pcie_rp6 on
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# Card reader
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device pci 00.0 on end
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register "PcieRpEnable[5]" = "true"
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register "PcieRpLtrEnable[5]" = "true"
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register "PcieClkSrcUsage[2]" = "5"
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register "PcieClkSrcClkReq[2]" = "2"
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end
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device ref pcie_rp9 on
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# SSD2 - PCIe mode
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register "PcieRpEnable[8]" = "true"
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register "PcieRpLtrEnable[8]" = "true"
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register "PcieClkSrcUsage[0]" = "8"
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register "PcieClkSrcClkReq[0]" = "0"
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@ -112,28 +112,24 @@ chip soc/intel/tigerlake
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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# Enable NVMe PCIE 9 using clk 0
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register "PcieRpEnable[8]" = "1"
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# NVMe PCIE 9 using clk 0
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[0]" = "8"
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register "PcieClkSrcClkReq[0]" = "0"
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register "PcieRpSlotImplemented[8]" = "1"
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# Enable Optane PCIE 11 using clk 0
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register "PcieRpEnable[10]" = "1"
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# Optane PCIE 11 using clk 0
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register "PcieRpLtrEnable[10]" = "1"
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register "HybridStorageMode" = "0"
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register "PcieRpSlotImplemented[10]" = "1"
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# Enable SD Card PCIE 8 using clk 3
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register "PcieRpEnable[7]" = "1"
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# SD Card PCIE 8 using clk 3
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register "PcieRpLtrEnable[7]" = "1"
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register "PcieRpHotPlug[7]" = "1"
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register "PcieClkSrcUsage[3]" = "7"
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register "PcieClkSrcClkReq[3]" = "3"
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# Enable WLAN PCIE 7 using clk 1
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register "PcieRpEnable[6]" = "1"
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# WLAN PCIE 7 using clk 1
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register "PcieRpLtrEnable[6]" = "1"
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register "PcieClkSrcUsage[1]" = "6"
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register "PcieClkSrcClkReq[1]" = "1"
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@ -469,7 +465,6 @@ chip soc/intel/tigerlake
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device ref i2c3 on end
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device ref heci1 on end
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device ref sata on end
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device ref pcie_rp1 on end
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device ref pcie_rp7 on end
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device ref pcie_rp8 on
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probe DB_SD SD_GL9755S
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@ -5,8 +5,7 @@ chip soc/intel/tigerlake
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register "DdiPort2Hpd" = "0"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
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# Enable EMMC PCIE 5 using clk 5
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register "PcieRpEnable[4]" = "1"
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# EMMC PCIE 5 using clk 5
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpHotPlug[4]" = "1"
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register "PcieClkSrcUsage[5]" = "4"
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@ -5,8 +5,7 @@ chip soc/intel/tigerlake
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register "DdiPort2Hpd" = "0"
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
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# Enable EMMC PCIE 5 using clk 5
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register "PcieRpEnable[4]" = "1"
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# EMMC PCIE 5 using clk 5
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpHotPlug[4]" = "1"
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register "PcieClkSrcUsage[5]" = "4"
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@ -12,13 +12,11 @@ chip soc/intel/tigerlake
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register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
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# Disable WLAN PCIE 7
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register "PcieRpEnable[6]" = "0"
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register "PcieRpLtrEnable[6]" = "0"
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register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
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register "PcieRpSlotImplemented[6]" = "1"
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# Disable SD Card PCIE 8
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register "PcieRpEnable[7]" = "0"
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register "PcieRpLtrEnable[7]" = "0"
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register "PcieRpHotPlug[7]" = "0"
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register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
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@ -102,6 +100,16 @@ chip soc/intel/tigerlake
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probe AUDIO MAX98360_ALC5682I_I2S
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probe AUDIO RT1011_ALC5682I_I2S
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end
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device ref pcie_rp7 off end
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device ref pcie_rp8 off
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# override-devicetree rules say it's only
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# the same device if it has the same probes:
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probe DB_SD SD_GL9755S
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probe DB_SD SD_RTS5261
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probe DB_SD SD_RTS5227S
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probe DB_SD SD_GL9750
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probe DB_SD SD_OZ711LV2LN
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end
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device ref pcie_rp9 on
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chip soc/intel/common/block/pcie/rtd3
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)"
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@ -37,10 +37,6 @@ chip soc/intel/tigerlake
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpEnable[10]" = "1"
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register "PcieRpSlotImplemented[2]" = "1"
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register "PcieRpSlotImplemented[3]" = "1"
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register "PcieRpSlotImplemented[8]" = "1"
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@ -38,10 +38,6 @@ chip soc/intel/tigerlake
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# EC memory map range is 0x900-0x9ff
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register "gen3_dec" = "0x00fc0901"
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register "PcieRpEnable[2]" = "1"
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register "PcieRpEnable[3]" = "1"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpEnable[10]" = "1"
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register "PcieRpSlotImplemented[2]" = "1"
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register "PcieRpSlotImplemented[3]" = "1"
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register "PcieRpSlotImplemented[8]" = "1"
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@ -133,7 +133,6 @@ chip soc/intel/tigerlake
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device ref uart2 on end
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device ref pcie_rp9 on
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register "HybridStorageMode" = "0"
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[3]" = "0x08"
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register "PcieClkSrcClkReq[3]" = "3"
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@ -53,21 +53,18 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp5 on
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# PCIe root port #5 x1, Clock 5 (GLAN)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieClkSrcUsage[5]" = "4"
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register "PcieClkSrcClkReq[5]" = "5"
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end
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device ref pcie_rp7 on
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# PCIe root port #7 x1, Clock 7 (CARD)
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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register "PcieClkSrcUsage[7]" = "6"
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register "PcieClkSrcClkReq[7]" = "7"
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end
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device ref pcie_rp8 on
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# PCIe root port #8 x1, Clock 8 (WLAN)
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register "PcieRpEnable[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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register "PcieClkSrcUsage[8]" = "7"
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register "PcieClkSrcClkReq[8]" = "8"
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@ -75,7 +72,6 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp9 on
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# PCIe root port #9 x4, Clock 9 (SSD1)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[9]" = "8"
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register "PcieClkSrcClkReq[9]" = "9"
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@ -53,21 +53,18 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp5 on
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# PCIe root port #5 x1, Clock 8 (GLAN)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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#register "PcieClkSrcUsage[8]" = "4"
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register "PcieClkSrcClkReq[8]" = "8"
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end
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device ref pcie_rp7 on
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# PCIe root port #7 x1, Clock 3 (CARD)
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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register "PcieClkSrcUsage[3]" = "6"
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register "PcieClkSrcClkReq[3]" = "3"
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end
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device ref pcie_rp8 on
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# PCIe root port #8 x1, Clock 2 (WLAN)
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register "PcieRpEnable[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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register "PcieClkSrcUsage[2]" = "7"
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register "PcieClkSrcClkReq[2]" = "2"
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end
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device ref pcie_rp9 on
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# PCIe root port #9 x4, Clock 10 (SSD2)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[10]" = "8"
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register "PcieClkSrcClkReq[10]" = "10"
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end
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device ref pcie_rp5 on
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# PCIe root port #5 x1, Clock 8 (GLAN)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieClkSrcUsage[8]" = "4"
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register "PcieClkSrcClkReq[8]" = "8"
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end
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device ref pcie_rp6 on
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# PCIe root port #6 x1, Clock 10 (CARD)
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register "PcieRpEnable[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieClkSrcUsage[10]" = "5"
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register "PcieClkSrcClkReq[10]" = "10"
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end
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device ref pcie_rp8 on
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# PCIe root port #8 x1, Clock 2 (WLAN)
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register "PcieRpEnable[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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register "PcieClkSrcUsage[2]" = "7"
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register "PcieClkSrcClkReq[2]" = "2"
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@ -84,7 +81,6 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp9 on
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# PCIe root port #9 x4, Clock 6 (SSD2)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[6]" = "8"
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register "PcieClkSrcClkReq[6]" = "6"
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@ -141,14 +141,12 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp6 on
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# PCIe root port #6 x1, Clock 2 (CARD)
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register "PcieRpEnable[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieClkSrcUsage[2]" = "5"
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register "PcieClkSrcClkReq[2]" = "2"
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end
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device ref pcie_rp7 on
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# PCIe root port #7 x1, Clock 3 (GLAN)
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register "PcieRpEnable[6]" = "1"
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register "PcieRpLtrEnable[6]" = "1"
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register "PcieClkSrcUsage[3]" = "6"
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register "PcieClkSrcClkReq[3]" = "3"
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@ -161,7 +159,6 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp8 on
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# PCIe root port #8 x1, Clock 1 (WLAN)
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register "PcieRpEnable[7]" = "1"
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register "PcieRpLtrEnable[7]" = "1"
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register "PcieClkSrcUsage[1]" = "7"
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register "PcieClkSrcClkReq[1]" = "1"
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@ -169,7 +166,6 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp9 on
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# PCIe root port #9 x4, Clock 4 (SSD0)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[4]" = "8"
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register "PcieClkSrcClkReq[4]" = "4"
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@ -141,7 +141,6 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp5 on
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# PCIe root port #5 x4, Clock 2 (NVIDIA GPU)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieClkSrcUsage[2]" = "4"
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register "PcieClkSrcClkReq[2]" = "2"
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end
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device ref pcie_rp9 on
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# PCIe root port #9 x1, Clock 3 (CARD)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[3]" = "8"
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register "PcieClkSrcClkReq[3]" = "3"
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end
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device ref pcie_rp10 on
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# PCIe root port #10 x1, Clock 4 (GLAN)
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register "PcieRpEnable[9]" = "1"
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register "PcieRpLtrEnable[9]" = "1"
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register "PcieClkSrcUsage[4]" = "9"
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register "PcieClkSrcClkReq[4]" = "4"
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end
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device ref pcie_rp11 on
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# PCIe root port #11 x1, Clock 1 (WLAN)
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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register "PcieClkSrcUsage[1]" = "10"
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register "PcieClkSrcClkReq[1]" = "1"
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@ -118,7 +118,6 @@ chip soc/intel/tigerlake
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end
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device ref pcie_rp3 on
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# PCIe root port #3 x1, Clock 1 (WLAN)
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register "PcieRpEnable[2]" = "1"
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register "PcieRpLtrEnable[2]" = "1"
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register "PcieClkSrcUsage[1]" = "2"
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register "PcieClkSrcClkReq[1]" = "1"
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end
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device ref pcie_rp6 on
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# PCIe root port #6 x1, Clock 2 (CARD)
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register "PcieRpEnable[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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register "PcieClkSrcUsage[2]" = "5"
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register "PcieClkSrcClkReq[2]" = "2"
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device ref pcie_rp9 on
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# PCIe root port #9 x4, Clock 0 (SSD2)
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# Despite the name, SSD1_CLKREQ# is used for SSD2
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieClkSrcUsage[0]" = "8"
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register "PcieClkSrcClkReq[0]" = "0"
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romstage-y += espi.c
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romstage-y += meminit.c
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romstage-y += pcie_rp.c
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romstage-y += reset.c
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ramstage-y += acpi.c
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@ -258,7 +258,6 @@ struct soc_intel_tigerlake_config {
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uint8_t PchHdaIDispCodecDisconnect;
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/* PCIe Root Ports */
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uint8_t PcieRpEnable[CONFIG_MAX_ROOT_PORTS];
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uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS];
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/* Implemented as slot or built-in? */
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uint8_t PcieRpSlotImplemented[CONFIG_MAX_ROOT_PORTS];
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@ -9,6 +9,7 @@
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#include <fsp/util.h>
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#include <gpio.h>
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#include <intelblocks/cpulib.h>
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#include <intelblocks/pcie_rp.h>
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#include <option.h>
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#include <soc/iomap.h>
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#include <soc/msr.h>
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const struct soc_intel_tigerlake_config *config)
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{
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unsigned int i;
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uint32_t cpu_id, mask = 0;
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uint32_t cpu_id;
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m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING));
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m_cfg->CpuRatio = (flex_ratio.lo >> 8) & 0xff;
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}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
|
||||
if (config->PcieRpEnable[i])
|
||||
mask |= (1 << i);
|
||||
}
|
||||
m_cfg->PcieRpEnableMask = mask;
|
||||
m_cfg->PcieRpEnableMask = pcie_rp_enable_mask(soc_get_pch_rp_groups());
|
||||
|
||||
memcpy(m_cfg->PcieClkSrcUsage, config->PcieClkSrcUsage,
|
||||
sizeof(config->PcieClkSrcUsage));
|
||||
|
|
Loading…
Reference in New Issue