GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ibexpeak/thermal: set temperature target in early init. 

Properly determine temperature target and set it in early
init rather than hardcoding it in late init.

Change-Id: Ie763f205890674a9dd1d9c5974caaccdd67cea14
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5264
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Vladimir Serbinenko 2014-02-19 22:02:51 +01:00
parent 10b3974811
commit 2bebc80166
2 changed files with 9 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/southbridge/intel/ibexpeak/early_thermal.c
View File

@ -20,12 +20,15 @@
#include <arch/io.h>
#include "pch.h"
#include "cpu/intel/model_2065x/model_2065x.h"
#include <cpu/x86/msr.h>
/* Early thermal init, must be done prior to giving ME its memory
which is done at the end of raminit. */
void early_thermal_init(void)
{
device_t dev;
msr_t msr;
dev = PCI_DEV(0x0, 0x1f, 0x6);
@ -38,6 +41,12 @@ void early_thermal_init(void)
pci_read_config32(dev, 0x40) | 5);
/* Perform init. */
/* Configure TJmax. */
msr = rdmsr(MSR_TEMPERATURE_TARGET);
write16(0x40000012, ((msr.lo >> 16) & 0xff) << 6);
/* Northbridge temperature slope and offset. */
write16(0x40000016, 0x7746);
/* Enable thermal data reporting, processor, PCH and northbridge. */
write16(0x4000001a, (read16(0x4000001a) & ~0xf) | 0x10f0);
/* Disable temporary BAR. */

3
src/southbridge/intel/ibexpeak/thermal.c
View File

@ -37,9 +37,6 @@ static void thermal_init(struct device *dev)
write32(res->base + 4, 0x3a2b);
write8(res->base + 0xe, 0x40);
write32(res->base + 0x12, 0x1a40);
write16(res->base + 0x16, 0x7746);
write16(res->base + 0x1a, 0x10f0);
write16(res->base + 0x56, 0xffff);
write16(res->base + 0x64, 0xffff);
write16(res->base + 0x66, 0xffff);