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util/inteltool: Add support for Sunrise Point LP 

Used documents:
334658 (Sunrise Point-LP I/O datasheet vol. 1)
334659 (Sunrise Point-LP I/O datasheet vol. 2)
332690 (Sunrise Point I/O datasheet vol. 1)

Change-Id: I16237ffc9a225b46271f2a51d77a7f28dfc36138
Signed-off-by: Felix Singer <migy@darmstadt.ccc.de>
Reviewed-on: https://review.coreboot.org/c/28623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Matthew Garrett 2018-07-23 21:09:47 -07:00 committed by Felix Held
parent 6ece0adf8c
commit 2bf28e52ee
10 changed files with 319 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
util/inteltool/ahci.c
View File

@ -67,7 +67,8 @@ int print_ahci(struct pci_dev *ahci)
} }
printf("\n============= AHCI Registers ==============\n\n"); printf("\n============= AHCI Registers ==============\n\n");
if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA) if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA ||
ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA)
mmio_size = 0x800; mmio_size = 0x800;
else else
mmio_size = 0x400; mmio_size = 0x400;
@ -96,7 +97,8 @@ int print_ahci(struct pci_dev *ahci)
print_port(mmio, i); print_port(mmio, i);
} }
if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA) { if (ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA ||
ahci->device_id == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA) {
puts("\nOther registers:"); puts("\nOther registers:");
for (i = 0x500; i < mmio_size; i += 4) { for (i = 0x500; i < mmio_size; i += 4) {
if (MMIO(i)) if (MMIO(i))

6
util/inteltool/gpio.c
View File

@ -1026,6 +1026,12 @@ int print_gpios(struct pci_dev *sb, int show_all, int show_diffs)
break; break;
case PCI_DEVICE_ID_INTEL_B150: case PCI_DEVICE_ID_INTEL_B150:
case PCI_DEVICE_ID_INTEL_CM236: case PCI_DEVICE_ID_INTEL_CM236:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
print_gpio_groups(sb); print_gpio_groups(sb);
return 0; return 0;
case PCI_DEVICE_ID_INTEL_82371XX: case PCI_DEVICE_ID_INTEL_82371XX:

243
util/inteltool/gpio_groups.c
View File

@ -52,7 +52,7 @@ static const char *const sunrise_group_a_names[] = {
"GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK", "GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
"GPP_A10", "CLKOUT_LPC1", "n/a", "n/a", "GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
"GPP_A11", "PME#", "n/a", "n/a", "GPP_A11", "PME#", "n/a", "n/a",
"GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#", "GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
"GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a", "GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
"GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#", "GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
"GPP_A15", "SUS_ACK#", "n/a", "n/a", "GPP_A15", "SUS_ACK#", "n/a", "n/a",
@ -73,6 +73,40 @@ static const struct gpio_group sunrise_group_a = {
.pad_names = sunrise_group_a_names, .pad_names = sunrise_group_a_names,
}; };
static const char *const sunrise_lp_group_a_names[] = {
"GPP_A0", "RCIN#", "n/a", "n/a",
"GPP_A1", "LAD0", "n/a", "ESPI_IO0",
"GPP_A2", "LAD1", "n/a", "ESPI_IO1",
"GPP_A3", "LAD2", "n/a", "ESPI_IO2",
"GPP_A4", "LAD3", "n/a", "ESPI_IO3",
"GPP_A5", "LFRAME#", "n/a", "ESPI_CS#",
"GPP_A6", "SERIRQ", "n/a", "n/a",
"GPP_A7", "PIRQA#", "n/a", "n/a",
"GPP_A8", "CLKRUN#", "n/a", "n/a",
"GPP_A9", "CLKOUT_LPC0", "n/a", "ESPI_CLK",
"GPP_A10", "CLKOUT_LPC1", "n/a", "n/a",
"GPP_A11", "PME#", "n/a", "n/a",
"GPP_A12", "BM_BUSY#", "ISH_GP6", "SX_EXIT_HOLDOFF#",
"GPP_A13", "SUSWARN#/SUSPWRDNACK", "n/a", "n/a",
"GPP_A14", "SUS_STAT#", "n/a", "ESPI_RESET#",
"GPP_A15", "SUS_ACK#", "n/a", "n/a",
"GPP_A16", "SD_1P8_SEL", "n/a", "n/a",
"GPP_A17", "SD_PWR_EN#", "ISH_GP7", "n/a",
"GPP_A18", "ISH_GP0", "n/a", "n/a",
"GPP_A19", "ISH_GP1", "n/a", "n/a",
"GPP_A20", "ISH_GP2", "n/a", "n/a",
"GPP_A21", "ISH_GP3", "n/a", "n/a",
"GPP_A22", "ISH_GP4", "n/a", "n/a",
"GPP_A23", "ISH_GP5", "n/a", "n/a",
};
static const struct gpio_group sunrise_lp_group_a = {
.display = "------- GPIO group GPP_A -------",
.pad_count = ARRAY_SIZE(sunrise_lp_group_a_names) / 4,
.func_count = 4,
.pad_names = sunrise_lp_group_a_names,
};
static const char *const sunrise_group_b_names[] = { static const char *const sunrise_group_b_names[] = {
"GPP_B0", "n/a", "n/a", "n/a", "GPP_B0", "n/a", "n/a", "n/a",
"GPP_B1", "n/a", "n/a", "n/a", "GPP_B1", "n/a", "n/a", "n/a",
@ -96,7 +130,7 @@ static const char *const sunrise_group_b_names[] = {
"GPP_B19", "GSPI1_CS#", "n/a", "n/a", "GPP_B19", "GSPI1_CS#", "n/a", "n/a",
"GPP_B20", "GSPI1_CLK", "n/a", "n/a", "GPP_B20", "GSPI1_CLK", "n/a", "n/a",
"GPP_B21", "GSPI1_MISO", "n/a", "n/a", "GPP_B21", "GSPI1_MISO", "n/a", "n/a",
"GPP_B22", "GSPIO_MOSI", "n/a", "n/a", "GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
"GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a", "GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
}; };
@ -107,10 +141,48 @@ static const struct gpio_group sunrise_group_b = {
.pad_names = sunrise_group_b_names, .pad_names = sunrise_group_b_names,
}; };
static const char *const sunrise_lp_group_b_names[] = {
"GPP_B0", "CORE_VID0", "n/a", "n/a",
"GPP_B1", "CORE_VID1", "n/a", "n/a",
"GPP_B2", "VRALERT#", "n/a", "n/a",
"GPP_B3", "CPU_GP2", "n/a", "n/a",
"GPP_B4", "CPU_GP3", "n/a", "n/a",
"GPP_B5", "SRCCLKREQ0#", "n/a", "n/a",
"GPP_B6", "SRCCLKREQ1#", "n/a", "n/a",
"GPP_B7", "SRCCLKREQ2#", "n/a", "n/a",
"GPP_B8", "SRCCLKREQ3#", "n/a", "n/a",
"GPP_B9", "SRCCLKREQ4#", "n/a", "n/a",
"GPP_B10", "SRCCLKREQ5#", "n/a", "n/a",
"GPP_B11", "EXT_PWR_GATE#", "n/a", "n/a",
"GPP_B12", "SLP_S0#", "n/a", "n/a",
"GPP_B13", "PLTRST#", "n/a", "n/a",
"GPP_B14", "SPKR", "n/a", "n/a",
"GPP_B15", "GSPI0_CS#", "n/a", "n/a",
"GPP_B16", "GSPI0_CLK", "n/a", "n/a",
"GPP_B17", "GSPI0_MISO", "n/a", "n/a",
"GPP_B18", "GSPI0_MOSI", "n/a", "n/a",
"GPP_B19", "GSPI1_CS#", "n/a", "n/a",
"GPP_B20", "GSPI1_CLK", "n/a", "n/a",
"GPP_B21", "GSPI1_MISO", "n/a", "n/a",
"GPP_B22", "GSPI1_MOSI", "n/a", "n/a",
"GPP_B23", "SML1ALERT#", "PCHHOT#", "n/a",
};
static const struct gpio_group sunrise_lp_group_b = {
.display = "------- GPIO Group GPP_B -------",
.pad_count = ARRAY_SIZE(sunrise_lp_group_b_names) / 4,
.func_count = 4,
.pad_names = sunrise_lp_group_b_names,
};
static const struct gpio_group *const sunrise_community_ab_groups[] = { static const struct gpio_group *const sunrise_community_ab_groups[] = {
&sunrise_group_a, &sunrise_group_b, &sunrise_group_a, &sunrise_group_b,
}; };
static const struct gpio_group *const sunrise_lp_community_ab_groups[] = {
&sunrise_lp_group_a, &sunrise_lp_group_b,
};
static const struct gpio_community sunrise_community_ab = { static const struct gpio_community sunrise_community_ab = {
.name = "------- GPIO Community 0 -------", .name = "------- GPIO Community 0 -------",
.pcr_port_id = 0xaf, .pcr_port_id = 0xaf,
@ -118,6 +190,13 @@ static const struct gpio_community sunrise_community_ab = {
.groups = sunrise_community_ab_groups, .groups = sunrise_community_ab_groups,
}; };
static const struct gpio_community sunrise_lp_community_ab = {
.name = "------- GPIO Community 0 -------",
.pcr_port_id = 0xaf,
.group_count = ARRAY_SIZE(sunrise_lp_community_ab_groups),
.groups = sunrise_lp_community_ab_groups,
};
static const char *const sunrise_group_c_names[] = { static const char *const sunrise_group_c_names[] = {
"GPP_C0", "SMBCLK", "n/a", "n/a", "GPP_C0", "SMBCLK", "n/a", "n/a",
"GPP_C1", "SMBDATA", "n/a", "n/a", "GPP_C1", "SMBDATA", "n/a", "n/a",
@ -157,7 +236,7 @@ static const char *const sunrise_group_d_names[] = {
"GPP_D1", "n/a", "n/a", "n/a", "GPP_D1", "n/a", "n/a", "n/a",
"GPP_D2", "n/a", "n/a", "n/a", "GPP_D2", "n/a", "n/a", "n/a",
"GPP_D3", "n/a", "n/a", "n/a", "GPP_D3", "n/a", "n/a", "n/a",
"GPP_D4", "ISH_I2C2_SDA", "I2C2_SDA", "n/a", "GPP_D4", "ISH_I2C2_SDA", "I2C3_SDA", "n/a",
"GPP_D5", "I2S_SFRM", "n/a", "n/a", "GPP_D5", "I2S_SFRM", "n/a", "n/a",
"GPP_D6", "I2S_TXD", "n/a", "n/a", "GPP_D6", "I2S_TXD", "n/a", "n/a",
"GPP_D7", "I2S_RXD", "n/a", "n/a", "GPP_D7", "I2S_RXD", "n/a", "n/a",
@ -186,6 +265,40 @@ static const struct gpio_group sunrise_group_d = {
.pad_names = sunrise_group_d_names, .pad_names = sunrise_group_d_names,
}; };
static const char *const sunrise_lp_group_d_names[] = {
"GPP_D0", "SPI1_CS#", "n/a", "n/a",
"GPP_D1", "SPI1_CLK", "n/a", "n/a",
"GPP_D2", "SPI1_MISO", "n/a", "n/a",
"GPP_D3", "SPI1_MOSI", "n/a", "n/a",
"GPP_D4", "FLASHTRIG", "n/a", "n/a",
"GPP_D5", "ISH_I2C0_SDA", "n/a", "n/a",
"GPP_D6", "ISH_I2C0_SCL", "n/a", "n/a",
"GPP_D7", "ISH_I2C1_SDA", "n/a", "n/a",
"GPP_D8", "ISH_I2C1_SCL", "n/a", "n/a",
"GPP_D9", "n/a", "n/a", "n/a",
"GPP_D10", "n/a", "n/a", "n/a",
"GPP_D11", "n/a", "n/a", "n/a",
"GPP_D12", "n/a", "n/a", "n/a",
"GPP_D13", "ISH_UART0_RXD", "n/a", "n/a",
"GPP_D14", "ISH_UART0_TXD", "n/a", "n/a",
"GPP_D15", "ISH_UART0_RTS#", "n/a", "n/a",
"GPP_D16", "ISH_UART0_CTS#", "n/a", "n/a",
"GPP_D17", "DMIC_CLK1", "n/a", "n/a",
"GPP_D18", "DMIC_DATA1", "n/a", "n/a",
"GPP_D19", "DMIC_CLK0", "n/a", "n/a",
"GPP_D20", "DMIC_DATA0", "n/a", "n/a",
"GPP_D21", "SPI1_IO2", "n/a", "n/a",
"GPP_D22", "SPI1_IO3", "n/a", "n/a",
"GPP_D23", "I2S_MCLK", "n/a", "n/a",
};
static const struct gpio_group sunrise_lp_group_d = {
.display = "------- GPIO Group GPP_D -------",
.pad_count = ARRAY_SIZE(sunrise_lp_group_d_names) / 4,
.func_count = 4,
.pad_names = sunrise_lp_group_d_names,
};
static const char *const sunrise_group_e_names[] = { static const char *const sunrise_group_e_names[] = {
"GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a", "GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
"GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a", "GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
@ -209,6 +322,40 @@ static const struct gpio_group sunrise_group_e = {
.pad_names = sunrise_group_e_names, .pad_names = sunrise_group_e_names,
}; };
static const char *const sunrise_lp_group_e_names[] = {
"GPP_E0", "SATAXPCIE0", "SATAGP0", "n/a",
"GPP_E1", "SATAXPCIE1", "SATAGP1", "n/a",
"GPP_E2", "SATAXPCIE2", "SATAGP2", "n/a",
"GPP_E3", "CPU_GP0", "n/a", "n/a",
"GPP_E4", "SATA_DEVSLP0", "n/a", "n/a",
"GPP_E5", "SATA_DEVSLP1", "n/a", "n/a",
"GPP_E6", "SATA_DEVSLP2", "n/a", "n/a",
"GPP_E7", "CPU_GP1", "n/a", "n/a",
"GPP_E8", "SATALED#", "n/a", "n/a",
"GPP_E9", "USB2_OC0#", "n/a", "n/a",
"GPP_E10", "USB2_OC1#", "n/a", "n/a",
"GPP_E11", "USB2_OC2#", "n/a", "n/a",
"GPP_E12", "USB2_OC3#", "n/a", "n/a",
"GPP_E13", "DDPB_HPD0", "n/a", "n/a",
"GPP_E14", "DDPC_HPD1", "n/a", "n/a",
"GPP_E15", "DDPD_HPD2", "n/a", "n/a",
"GPP_E16", "DDPE_HPD3", "n/a", "n/a",
"GPP_E17", "EDP_HPD", "n/a", "n/a",
"GPP_E18", "DDPB_CTRLCLK", "n/a", "n/a",
"GPP_E19", "DDPB_CTRLDATA", "n/a", "n/a",
"GPP_E20", "DDPC_CTRLCLK", "n/a", "n/a",
"GPP_E21", "DDPC_CTRLDATA", "n/a", "n/a",
"GPP_E22", "n/a", "n/a", "n/a",
"GPP_E23", "n/a", "n/a", "n/a",
};
static const struct gpio_group sunrise_lp_group_e = {
.display = "------- GPIO Group GPP_E -------",
.pad_count = ARRAY_SIZE(sunrise_lp_group_e_names) / 4,
.func_count = 4,
.pad_names = sunrise_lp_group_e_names,
};
static const char *const sunrise_group_f_names[] = { static const char *const sunrise_group_f_names[] = {
"GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a", "GPP_F0", "SATAXPCIE3", "SATAGP3", "n/a",
"GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a", "GPP_F1", "SATAXPCIE4", "SATAGP4", "n/a",
@ -243,6 +390,40 @@ static const struct gpio_group sunrise_group_f = {
.pad_names = sunrise_group_f_names, .pad_names = sunrise_group_f_names,
}; };
static const char *const sunrise_lp_group_f_names[] = {
"GPP_F0", "I2S2_SCLK", "n/a", "n/a",
"GPP_F1", "I2S2_SFRM", "n/a", "n/a",
"GPP_F2", "I2S2_TXD", "n/a", "n/a",
"GPP_F3", "I2S2_RXD", "n/a", "n/a",
"GPP_F4", "I2C2_SDA", "n/a", "n/a",
"GPP_F5", "I2C2_SCL", "n/a", "n/a",
"GPP_F6", "I2C3_SDA", "n/a", "n/a",
"GPP_F7", "I2C3_SCL", "n/a", "n/a",
"GPP_F8", "I2C4_SDA", "n/a", "n/a",
"GPP_F9", "I2C4_SCL", "n/a", "n/a",
"GPP_F10", "I2C5_SDA", "ISH_I2C2_SDA", "n/a",
"GPP_F11", "I2C5_SCL", "ISH_I2C2_SCL", "n/a",
"GPP_F12", "EMMC_CMD", "n/a", "n/a",
"GPP_F13", "EMMC_DATA0", "n/a", "n/a",
"GPP_F14", "EMMC_DATA1", "n/a", "n/a",
"GPP_F15", "EMMC_DATA2", "n/a", "n/a",
"GPP_F16", "EMMC_DATA3", "n/a", "n/a",
"GPP_F17", "EMMC_DATA4", "n/a", "n/a",
"GPP_F18", "EMMC_DATA5", "n/a", "n/a",
"GPP_F19", "EMMC_DATA6", "n/a", "n/a",
"GPP_F20", "EMMC_DATA7", "n/a", "n/a",
"GPP_F21", "EMMC_RCLK", "n/a", "n/a",
"GPP_F22", "EMMC_CLK", "n/a", "n/a",
"GPP_F23", "n/a", "n/a", "n/a",
};
static const struct gpio_group sunrise_lp_group_f = {
.display = "------- GPIO Group GPP_F -------",
.pad_count = ARRAY_SIZE(sunrise_lp_group_f_names) / 4,
.func_count = 4,
.pad_names = sunrise_lp_group_f_names,
};
static const char *const sunrise_group_g_names[] = { static const char *const sunrise_group_g_names[] = {
"GPP_G0", "FAN_TACH_0", "n/a", "n/a", "GPP_G0", "FAN_TACH_0", "n/a", "n/a",
"GPP_G1", "FAN_TACH_1", "n/a", "n/a", "GPP_G1", "FAN_TACH_1", "n/a", "n/a",
@ -277,6 +458,24 @@ static const struct gpio_group sunrise_group_g = {
.pad_names = sunrise_group_g_names, .pad_names = sunrise_group_g_names,
}; };
static const char *const sunrise_lp_group_g_names[] = {
"GPP_G0", "SD_CMD", "n/a", "n/a",
"GPP_G1", "SD_DATA0", "n/a", "n/a",
"GPP_G2", "SD_DATA1", "n/a", "n/a",
"GPP_G3", "SD_DATA2", "n/a", "n/a",
"GPP_G4", "SD_DATA3", "n/a", "n/a",
"GPP_G5", "SD_CD#", "n/a", "n/a",
"GPP_G6", "SD_CLK", "n/a", "n/a",
"GPP_G7", "SD_WP", "n/a", "n/a",
};
static const struct gpio_group sunrise_lp_group_g = {
.display = "------- GPIO Group GPP_G -------",
.pad_count = ARRAY_SIZE(sunrise_lp_group_g_names) / 4,
.func_count = 4,
.pad_names = sunrise_lp_group_g_names,
};
static const char *const sunrise_group_h_names[] = { static const char *const sunrise_group_h_names[] = {
"GPP_H0", "SRCCLKREQ6#", "n/a", "n/a", "GPP_H0", "SRCCLKREQ6#", "n/a", "n/a",
"GPP_H1", "SRCCLKREQ7#", "n/a", "n/a", "GPP_H1", "SRCCLKREQ7#", "n/a", "n/a",
@ -316,6 +515,10 @@ static const struct gpio_group *const sunrise_community_cdefgh_groups[] = {
&sunrise_group_f, &sunrise_group_g, &sunrise_group_h, &sunrise_group_f, &sunrise_group_g, &sunrise_group_h,
}; };
static const struct gpio_group *const sunrise_lp_community_cde_groups[] = {
&sunrise_group_c, &sunrise_lp_group_d, &sunrise_lp_group_e,
};
static const struct gpio_community sunrise_community_cdefgh = { static const struct gpio_community sunrise_community_cdefgh = {
.name = "------- GPIO Community 1 -------", .name = "------- GPIO Community 1 -------",
.pcr_port_id = 0xae, .pcr_port_id = 0xae,
@ -323,6 +526,13 @@ static const struct gpio_community sunrise_community_cdefgh = {
.groups = sunrise_community_cdefgh_groups, .groups = sunrise_community_cdefgh_groups,
}; };
static const struct gpio_community sunrise_lp_community_cde = {
.name = "------- GPIO Community 1 -------",
.pcr_port_id = 0xae,
.group_count = ARRAY_SIZE(sunrise_lp_community_cde_groups),
.groups = sunrise_lp_community_cde_groups,
};
static const char *const sunrise_group_gpd_names[] = { static const char *const sunrise_group_gpd_names[] = {
"GPD0", "BATLOW#", "n/a", "n/a", "GPD0", "BATLOW#", "n/a", "n/a",
"GPD1", "ACPRESENT", "n/a", "n/a", "GPD1", "ACPRESENT", "n/a", "n/a",
@ -381,6 +591,10 @@ static const struct gpio_group *const sunrise_community_i_groups[] = {
&sunrise_group_i, &sunrise_group_i,
}; };
static const struct gpio_group *const sunrise_lp_community_fg_groups[] = {
&sunrise_lp_group_f, &sunrise_lp_group_g,
};
static const struct gpio_community sunrise_community_i = { static const struct gpio_community sunrise_community_i = {
.name = "------- GPIO Community 3 -------", .name = "------- GPIO Community 3 -------",
.pcr_port_id = 0xac, .pcr_port_id = 0xac,
@ -388,11 +602,24 @@ static const struct gpio_community sunrise_community_i = {
.groups = sunrise_community_i_groups, .groups = sunrise_community_i_groups,
}; };
static const struct gpio_community sunrise_lp_community_fg = {
.name = "------- GPIO Community 3 -------",
.pcr_port_id = 0xac,
.group_count = ARRAY_SIZE(sunrise_lp_community_fg_groups),
.groups = sunrise_lp_community_fg_groups,
};
static const struct gpio_community *const sunrise_communities[] = { static const struct gpio_community *const sunrise_communities[] = {
&sunrise_community_ab, &sunrise_community_cdefgh, &sunrise_community_ab, &sunrise_community_cdefgh,
&sunrise_community_gpd, &sunrise_community_i, &sunrise_community_gpd, &sunrise_community_i,
}; };
static const struct gpio_community *const sunrise_lp_communities[] = {
&sunrise_lp_community_ab, &sunrise_lp_community_cde,
&sunrise_community_gpd, &sunrise_lp_community_fg,
};
static const char *decode_pad_mode(const struct gpio_group *const group, static const char *decode_pad_mode(const struct gpio_group *const group,
const size_t pad, const uint32_t dw0) const size_t pad, const uint32_t dw0)
{ {
@ -460,6 +687,16 @@ void print_gpio_groups(struct pci_dev *const sb)
communities = sunrise_communities; communities = sunrise_communities;
pcr_init(sb); pcr_init(sb);
break; break;
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
community_count = ARRAY_SIZE(sunrise_lp_communities);
communities = sunrise_lp_communities;
pcr_init(sb);
break;
default: default:
return; return;
} }

18
util/inteltool/inteltool.c
View File

@ -129,6 +129,12 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D2,
"6th generation (Skylake-S family) Core Processor (Desktop)" }, "6th generation (Skylake-S family) Core Processor (Desktop)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL, "Bay Trail" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U,
"7th generation (Kaby Lake family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y,
"7th generation (Kaby Lake family) Core Processor (Mobile)" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q,
"7th generation (Kaby Lake family) Core Processor (Mobile)" },
/* Southbridges (LPC controllers) */ /* Southbridges (LPC controllers) */
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10, "ICH10" },
@ -218,6 +224,18 @@ static const struct {
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_LPC, "Bay Trail" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE,
"Sunrise Point Desktop Engineering Sample" }, "Sunrise Point Desktop Engineering Sample" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE,
"Sunrise Point-LP U Base" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM,
"Sunrise Point-LP U Premium" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM,
"Sunrise Point-LP Y Premium" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE,
"Sunrise Point-LP U iHDCP 2.2 Base" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM,
"Sunrise Point-LP U iHDCP 2.2 Premium" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM,
"Sunrise Point-LP Y iHDCP 2.2 Premium" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H110, "H110" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_H170, "H170" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" }, { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Z170, "Z170" },

19
util/inteltool/inteltool.h
View File

@ -140,10 +140,17 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43
#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_PREM 0x9cc3
#define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP 0x9cc5
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_SATA 0xa102
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_P2SB 0xa120
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_PRE 0xa141
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SATA 0x9d03
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE 0x9d53
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM 0x9d58
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM 0x9d56
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE 0x9d50
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM 0x9d4e
#define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM 0x9d4b
#define PCI_DEVICE_ID_INTEL_H110 0xa143 #define PCI_DEVICE_ID_INTEL_H110 0xa143
#define PCI_DEVICE_ID_INTEL_H170 0xa144 #define PCI_DEVICE_ID_INTEL_H170 0xa144
#define PCI_DEVICE_ID_INTEL_Z170 0xa145 #define PCI_DEVICE_ID_INTEL_Z170 0xa145
@ -248,6 +255,10 @@ static inline uint32_t inl(unsigned port)
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M 0x1910 /* Skylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST 0x1918 /* Skylake (Workstation) */
#define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */ #define PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D 0x191f /* Skylake (Desktop) */
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U 0x5904 /* Kabylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y 0x590C /* Kabylake (Mobile) */
#define PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q 0x5914 /* Kabylake (Mobile) */
/* Intel GPUs */ /* Intel GPUs */
#define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982 #define PCI_DEVICE_ID_INTEL_G35_EXPRESS 0x2982

3
util/inteltool/memory.c
View File

@ -222,6 +222,9 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
mchbar_phys = pci_read_long(nb, 0x48); mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32; mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */ mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */

9
util/inteltool/pcie.c
View File

@ -267,6 +267,9 @@ int print_epbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe; epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32; epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
break; break;
@ -389,6 +392,9 @@ int print_dmibar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
dmi_registers = skylake_dmi_registers; dmi_registers = skylake_dmi_registers;
size = ARRAY_SIZE(skylake_dmi_registers); size = ARRAY_SIZE(skylake_dmi_registers);
dmibar_phys = pci_read_long(nb, 0x68); dmibar_phys = pci_read_long(nb, 0x68);
@ -495,6 +501,9 @@ int print_pciexbar(struct pci_dev *nb)
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_M:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D: case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_D:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_Y:
case PCI_DEVICE_ID_INTEL_CORE_7TH_GEN_U_Q:
pciexbar_reg = pci_read_long(nb, 0x60); pciexbar_reg = pci_read_long(nb, 0x60);
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32; pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
break; break;

6
util/inteltool/powermgt.c
View File

@ -745,6 +745,12 @@ int print_pmbase(struct pci_dev *sb, struct pci_access *pacc)
case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C224:
case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_C226:
case PCI_DEVICE_ID_INTEL_H81: case PCI_DEVICE_ID_INTEL_H81:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
pmbase = pci_read_word(sb, 0x40) & 0xff80; pmbase = pci_read_word(sb, 0x40) & 0xff80;
pm_registers = pch_pm_registers; pm_registers = pch_pm_registers;
size = ARRAY_SIZE(pch_pm_registers); size = ARRAY_SIZE(pch_pm_registers);

6
util/inteltool/rootcmplx.c
View File

@ -112,6 +112,12 @@ int print_rcba(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C224:
case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_C226:
case PCI_DEVICE_ID_INTEL_H81: case PCI_DEVICE_ID_INTEL_H81:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
break; break;
case PCI_DEVICE_ID_INTEL_ICH: case PCI_DEVICE_ID_INTEL_ICH:

12
util/inteltool/spi.c
View File

@ -175,6 +175,12 @@ int print_bioscntl(struct pci_dev *sb)
case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C224:
case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_C226:
case PCI_DEVICE_ID_INTEL_H81: case PCI_DEVICE_ID_INTEL_H81:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
bios_cntl = pci_read_byte(sb, 0xdc); bios_cntl = pci_read_byte(sb, 0xdc);
bios_cntl_register = pch_bios_cntl_registers; bios_cntl_register = pch_bios_cntl_registers;
size = ARRAY_SIZE(pch_bios_cntl_registers); size = ARRAY_SIZE(pch_bios_cntl_registers);
@ -303,6 +309,12 @@ int print_spibar(struct pci_dev *sb) {
case PCI_DEVICE_ID_INTEL_C224: case PCI_DEVICE_ID_INTEL_C224:
case PCI_DEVICE_ID_INTEL_C226: case PCI_DEVICE_ID_INTEL_C226:
case PCI_DEVICE_ID_INTEL_H81: case PCI_DEVICE_ID_INTEL_H81:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_BASE:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_U_IHDCP_PREM:
case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_Y_IHDCP_PREM:
spibaroffset = ICH9_SPIBAR; spibaroffset = ICH9_SPIBAR;
rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe; rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
size = ARRAY_SIZE(spi_bar_registers); size = ARRAY_SIZE(spi_bar_registers);