southbridge/amd/sr5650/sr5650.c: Update acpi_fill_ivrs
- Update lines to make them shorter than 80 chaacters - Update using #defines from acpi_ivrs.h Change-Id: I1bf6cdac00e28f5b0969fd8f98e37c66f8e43110 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16568 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
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@ -825,50 +825,62 @@ static unsigned long acpi_fill_ivrs(acpi_ivrs_t* ivrs, unsigned long current)
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device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (!nb_dev) {
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printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 device! IVRS table not generated...\n");
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printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
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"device! IVRS table not generated...\n");
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return (unsigned long)ivrs;
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}
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device_t iommu_dev = dev_find_slot(0, PCI_DEVFN(0, 2));
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if (!iommu_dev) {
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printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 IOMMU device! IVRS table not generated...\n");
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printk(BIOS_WARNING, "acpi_fill_ivrs: Unable to locate SR5650 "
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"IOMMU device! IVRS table not generated...\n");
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return (unsigned long)ivrs;
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}
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ivrs->iv_info = 0x0;
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ivrs->iv_info |= (0x40 << 15); /* Maximum supported virtual address size */
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ivrs->iv_info |= (0x34 << 8); /* Maximum supported physical address size */
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ivrs->iv_info = IVINFO_VA_SIZE_64_BITS | IVINFO_PA_SIZE_52_BITS;
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ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED;
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ivrs->ivhd.flags = IVHD_FLAG_ISOC |
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IVHD_FLAG_RES_PASS_PW |
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IVHD_FLAG_PASS_PW |
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IVHD_FLAG_IOTLB_SUP;
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ivrs->ivhd.type = 0x10;
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ivrs->ivhd.flags = 0x0e;
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// if (get_nb_rev(nb_dev) != REV_SR5650_A11) {
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ivrs->ivhd.flags |= 0x10; /* Enable ATS support on all revisions except A11 */
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// }
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ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd);
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ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8); /* BDF <bus>:00.2 */
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ivrs->ivhd.capability_offset = 0x40; /* Capability block 0x40 (type 0xf, "Secure device") */
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ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000;
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/* BDF <bus>:00.2 */
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ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8);
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/* Capability block 0x40 (type 0xf, "Secure device") */
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ivrs->ivhd.capability_offset = 0x40;
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ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) &
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0xffffc000;
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ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48);
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ivrs->ivhd.pci_segment_group = 0x0;
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ivrs->ivhd.iommu_info = 0x0;
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ivrs->ivhd.iommu_info |= (0x14 << 8);
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ivrs->ivhd.iommu_info |= (0x14 << IOMMU_INFO_UNIT_ID_SHIFT);
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ivrs->ivhd.iommu_feature_info = 0x0;
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/* Describe HPET */
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p = (uint8_t *)current;
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p[0] = 0x48; /* Entry type */
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p[1] = 0; /* Device */
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p[2] = 0; /* Bus */
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p[3] = 0xd7; /* Data */
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p[4] = 0x0; /* HPET number */
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p[5] = 0x14 << 3; /* HPET device */
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p[6] = nb_dev->bus->secondary; /* HPET bus */
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p[7] = 0x2; /* Variety */
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p[0] = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; /* Entry type */
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p[1] = 0; /* Device */
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p[2] = 0; /* Bus */
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p[3] = IVHD_DTE_LINT_1_PASS | /* DTE */
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IVHD_DTE_LINT_0_PASS |
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IVHD_DTE_SYS_MGT_INTX_NO_TRANS |
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IVHD_DTE_NMI_PASS |
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IVHD_DTE_EXT_INT_PASS |
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IVHD_DTE_INIT_PASS;
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p[4] = 0x0; /* HPET number */
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p[5] = 0x14 << 3; /* HPET device */
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p[6] = nb_dev->bus->secondary; /* HPET bus */
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p[7] = IVHD_SPECIAL_DEV_HPET; /* Variety */
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ivrs->ivhd.length += 8;
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current += 8;
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/* Describe PCI devices */
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add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, ¤t, &ivrs->ivhd.length);
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add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, ¤t,
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&ivrs->ivhd.length);
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/* Describe IOAPICs */
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unsigned long prev_current = current;
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